[PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE.

[PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE.

[Andrew Cooper]

Intercepting this MSR is pointless - The swapgs instruction does not cause a
vmexit, so the cached result of this is potentially stale after the next guest
instruction.  It is correctly saved and restored on vcpu context switch.

Furthermore, 64bit Windows writes to this MSR on every thread context switch,
so interception causes a substantial performance hit.

From: Paul Durrant <paul.durrant@citrix.com>
Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Keir Fraser <keir@xen.org>
CC: Jan Beulich <JBeulich@suse.com>
CC: Tim Deegan <tim@xen.org>
CC: Jun Nakajima <jun.nakajima@intel.com>
CC: Eddie Dong <eddie.dong@intel.com>
---
 xen/arch/x86/hvm/vmx/vmcs.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 290b42f..4aab971 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -950,6 +950,7 @@ static int construct_vmcs(struct vcpu *v)
 
         vmx_disable_intercept_for_msr(v, MSR_FS_BASE, MSR_TYPE_R | MSR_TYPE_W);
         vmx_disable_intercept_for_msr(v, MSR_GS_BASE, MSR_TYPE_R | MSR_TYPE_W);
+        vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE, MSR_TYPE_R | MSR_TYPE_W);
         vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_CS, MSR_TYPE_R | MSR_TYPE_W);
         vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_ESP, MSR_TYPE_R | MSR_TYPE_W);
         vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_EIP, MSR_TYPE_R | MSR_TYPE_W);
-- 
1.7.10.4

Re: [PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE.

[Tim Deegan]

At 14:02 +0000 on 14 Nov (1384434176), Andrew Cooper wrote:
> Intercepting this MSR is pointless - The swapgs instruction does not cause a
> vmexit, so the cached result of this is potentially stale after the next guest
> instruction.  It is correctly saved and restored on vcpu context switch.
> 
> Furthermore, 64bit Windows writes to this MSR on every thread context switch,
> so interception causes a substantial performance hit.
> 
> From: Paul Durrant <paul.durrant@citrix.com>
> Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Reviewed-by: Tim Deegan <tim@xen.org>

Re: [PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE.

[Nakajima, Jun]

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On Thu, Nov 14, 2013 at 8:01 AM, Tim Deegan <tim@xen.org> wrote:

> At 14:02 +0000 on 14 Nov (1384434176), Andrew Cooper wrote:
> > Intercepting this MSR is pointless - The swapgs instruction does not
> cause a
> > vmexit, so the cached result of this is potentially stale after the next
> guest
> > instruction.  It is correctly saved and restored on vcpu context switch.
> >
> > Furthermore, 64bit Windows writes to this MSR on every thread context
> switch,
> > so interception causes a substantial performance hit.
> >
> > From: Paul Durrant <paul.durrant@citrix.com>
> > Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
> > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
> Reviewed-by: Tim Deegan <tim@xen.org>
>

Acked-by: Jun Nakajima <jun.nakajima@intel.com>
-- 
Jun
Intel Open Source Technology Center

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