From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: xen-devel@lists.xen.org
Cc: keir@xen.org, suravee.suthikulpanit@amd.com,
andrew.cooper3@citrix.com, eddie.dong@intel.com,
dietmar.hahn@ts.fujitsu.com, JBeulich@suse.com,
jun.nakajima@intel.com, boris.ostrovsky@oracle.com
Subject: [PATCH v4 15/17] x86/VPMU: NMI-based VPMU support
Date: Tue, 21 Jan 2014 14:09:00 -0500 [thread overview]
Message-ID: <1390331342-3967-16-git-send-email-boris.ostrovsky@oracle.com> (raw)
In-Reply-To: <1390331342-3967-1-git-send-email-boris.ostrovsky@oracle.com>
Add support for using NMIs as PMU interrupts.
Most of processing is still performed by vpmu_do_interrupt(). However, since
certain operations are not NMI-safe we defer them to a softint that vpmu_do_interrupt()
will schedule:
* For PV guests that would be send_guest_vcpu_virq() and hvm_get_segment_register().
* For HVM guests it's VLAPIC accesses.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
xen/arch/x86/hvm/vpmu.c | 169 ++++++++++++++++++++++++++++++++++++++----------
1 file changed, 135 insertions(+), 34 deletions(-)
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index 214300d..e76b538 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -36,6 +36,7 @@
#include <asm/hvm/svm/svm.h>
#include <asm/hvm/svm/vmcb.h>
#include <asm/apic.h>
+#include <asm/nmi.h>
#include <public/xenpmu.h>
/*
@@ -48,33 +49,57 @@ static void parse_vpmu_param(char *s);
custom_param("vpmu", parse_vpmu_param);
static DEFINE_PER_CPU(struct vcpu *, last_vcpu);
+static DEFINE_PER_CPU(struct vcpu *, sampled_vcpu);
+
+uint32_t vpmu_apic_vector = PMU_APIC_VECTOR;
static void __init parse_vpmu_param(char *s)
{
- switch ( parse_bool(s) )
- {
- case 0:
- break;
- default:
- if ( !strcmp(s, "bts") )
- vpmu_mode |= XENPMU_FEATURE_INTEL_BTS << XENPMU_FEATURE_SHIFT;
- else if ( *s )
+ char *ss;
+
+ vpmu_mode = XENPMU_MODE_ON;
+ if (*s == '\0')
+ return;
+
+ do {
+ ss = strchr(s, ',');
+ if ( ss )
+ *ss = '\0';
+
+ switch (parse_bool(s) )
{
- printk("VPMU: unknown flag: %s - vpmu disabled!\n", s);
+ case 0:
+ vpmu_mode = XENPMU_MODE_OFF;
+ return;
+ case -1:
+ if ( !strcmp(s, "nmi") )
+ vpmu_apic_vector = APIC_DM_NMI;
+ else if ( !strcmp(s, "bts") )
+ vpmu_mode |= XENPMU_FEATURE_INTEL_BTS << XENPMU_FEATURE_SHIFT;
+ else if ( !strcmp(s, "priv") )
+ {
+ vpmu_mode &= ~XENPMU_MODE_ON;
+ vpmu_mode |= XENPMU_MODE_PRIV;
+ }
+ else
+ {
+ printk("VPMU: unknown flag: %s - vpmu disabled!\n", s);
+ vpmu_mode = XENPMU_MODE_OFF;
+ return;
+ }
+ default:
break;
}
- /* fall through */
- case 1:
- vpmu_mode |= XENPMU_MODE_ON;
- break;
- }
+
+ s = ss + 1;
+ } while ( ss );
}
void vpmu_lvtpc_update(uint32_t val)
{
struct vpmu_struct *vpmu = vcpu_vpmu(current);
- vpmu->hw_lapic_lvtpc = PMU_APIC_VECTOR | (val & APIC_LVT_MASKED);
+ vpmu->hw_lapic_lvtpc = vpmu_apic_vector | (val & APIC_LVT_MASKED);
/* Postpone APIC updates for PV guests if PMU interrupt is pending */
if ( !is_pv_domain(current->domain) ||
@@ -83,6 +108,24 @@ void vpmu_lvtpc_update(uint32_t val)
apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
}
+static void vpmu_send_nmi(struct vcpu *v)
+{
+ struct vlapic *vlapic = vcpu_vlapic(v);
+ u32 vlapic_lvtpc;
+ unsigned char int_vec;
+
+ if ( !is_vlapic_lvtpc_enabled(vlapic) )
+ return;
+
+ vlapic_lvtpc = vlapic_get_reg(vlapic, APIC_LVTPC);
+ int_vec = vlapic_lvtpc & APIC_VECTOR_MASK;
+
+ if ( GET_APIC_DELIVERY_MODE(vlapic_lvtpc) == APIC_MODE_FIXED )
+ vlapic_set_irq(vcpu_vlapic(v), int_vec, 0);
+ else
+ v->nmi_pending = 1;
+}
+
int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content)
{
struct vpmu_struct *vpmu = vcpu_vpmu(current);
@@ -134,6 +177,7 @@ int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
return 0;
}
+/* This routine may be called in NMI context */
int vpmu_do_interrupt(struct cpu_user_regs *regs)
{
struct vcpu *v = current;
@@ -214,9 +258,13 @@ int vpmu_do_interrupt(struct cpu_user_regs *regs)
memcpy(&v->arch.vpmu.xenpmu_data->pmu.r.regs,
gregs, sizeof(struct cpu_user_regs));
- hvm_get_segment_register(current, x86_seg_cs, &cs);
- gregs = &v->arch.vpmu.xenpmu_data->pmu.r.regs;
- gregs->cs = cs.attr.fields.dpl;
+ /* This is unsafe in NMI context, we'll do it in softint handler */
+ if ( !(vpmu_apic_vector & APIC_DM_NMI ) )
+ {
+ hvm_get_segment_register(current, x86_seg_cs, &cs);
+ gregs = &v->arch.vpmu.xenpmu_data->pmu.r.regs;
+ gregs->cs = cs.attr.fields.dpl;
+ }
}
v->arch.vpmu.xenpmu_data->domain_id = current->domain->domain_id;
@@ -227,29 +275,29 @@ int vpmu_do_interrupt(struct cpu_user_regs *regs)
apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc | APIC_LVT_MASKED);
vpmu->hw_lapic_lvtpc |= APIC_LVT_MASKED;
- send_guest_vcpu_virq(v, VIRQ_XENPMU);
+ if ( vpmu_apic_vector & APIC_DM_NMI )
+ {
+ per_cpu(sampled_vcpu, smp_processor_id()) = current;
+ raise_softirq(PMU_SOFTIRQ);
+ }
+ else
+ send_guest_vcpu_virq(v, VIRQ_XENPMU);
return 1;
}
else if ( vpmu->arch_vpmu_ops )
{
- struct vlapic *vlapic = vcpu_vlapic(v);
- u32 vlapic_lvtpc;
- unsigned char int_vec;
-
if ( !vpmu->arch_vpmu_ops->do_interrupt(regs) )
return 0;
- if ( !is_vlapic_lvtpc_enabled(vlapic) )
- return 1;
-
- vlapic_lvtpc = vlapic_get_reg(vlapic, APIC_LVTPC);
- int_vec = vlapic_lvtpc & APIC_VECTOR_MASK;
-
- if ( GET_APIC_DELIVERY_MODE(vlapic_lvtpc) == APIC_MODE_FIXED )
- vlapic_set_irq(vcpu_vlapic(v), int_vec, 0);
+ if ( vpmu_apic_vector & APIC_DM_NMI )
+ {
+ per_cpu(sampled_vcpu, smp_processor_id()) = current;
+ raise_softirq(PMU_SOFTIRQ);
+ }
else
- v->nmi_pending = 1;
+ vpmu_send_nmi(v);
+
return 1;
}
@@ -299,7 +347,7 @@ void vpmu_save(struct vcpu *v)
if ( vpmu->arch_vpmu_ops->arch_vpmu_save(v) )
vpmu_reset(vpmu, VPMU_CONTEXT_LOADED);
- apic_write(APIC_LVTPC, PMU_APIC_VECTOR | APIC_LVT_MASKED);
+ apic_write(APIC_LVTPC, vpmu_apic_vector | APIC_LVT_MASKED);
}
void vpmu_load(struct vcpu *v)
@@ -414,12 +462,50 @@ void vpmu_dump(struct vcpu *v)
vpmu->arch_vpmu_ops->arch_vpmu_dump(v);
}
+/* Process the softirq set by PMU NMI handler */
+static void pmu_softnmi(void)
+{
+ struct cpu_user_regs *regs;
+ struct vcpu *v, *sampled = per_cpu(sampled_vcpu, smp_processor_id());
+
+ if ( vpmu_mode & XENPMU_MODE_PRIV ||
+ sampled->domain->domain_id >= DOMID_FIRST_RESERVED )
+ v = dom0->vcpu[smp_processor_id() % dom0->max_vcpus];
+ else
+ {
+ if ( is_hvm_domain(sampled->domain) )
+ {
+ vpmu_send_nmi(sampled);
+ return;
+ }
+ v = sampled;
+ }
+
+ regs = &v->arch.vpmu.xenpmu_data->pmu.r.regs;
+ if ( !is_pv_domain(sampled->domain) )
+ {
+ struct segment_register cs;
+
+ hvm_get_segment_register(sampled, x86_seg_cs, &cs);
+ regs->cs = cs.attr.fields.dpl;
+ }
+
+ send_guest_vcpu_virq(v, VIRQ_XENPMU);
+}
+
+int pmu_nmi_interrupt(struct cpu_user_regs *regs, int cpu)
+{
+ return vpmu_do_interrupt(regs);
+}
+
+
static int pvpmu_init(struct domain *d, xen_pmu_params_t *params)
{
struct vcpu *v;
struct page_info *page;
uint64_t gmfn = params->d.val;
-
+ static int pvpmu_initted = 0;
+
if ( params->vcpu < 0 || params->vcpu >= d->max_vcpus )
return -EINVAL;
@@ -435,6 +521,21 @@ static int pvpmu_init(struct domain *d, xen_pmu_params_t *params)
return -EINVAL;
}
+ if ( !pvpmu_initted )
+ {
+ if (reserve_lapic_nmi() == 0)
+ set_nmi_callback(pmu_nmi_interrupt);
+ else
+ {
+ printk("Failed to reserve PMU NMI\n");
+ put_page(page);
+ return -EBUSY;
+ }
+ open_softirq(PMU_SOFTIRQ, pmu_softnmi);
+
+ pvpmu_initted = 1;
+ }
+
vpmu_initialise(v);
return 0;
--
1.8.1.4
next prev parent reply other threads:[~2014-01-21 19:09 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-21 19:08 [PATCH v4 00/17] x86/PMU: Xen PMU PV support Boris Ostrovsky
2014-01-21 19:08 ` [PATCH v4 01/17] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-01-24 14:16 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 02/17] x86/VPMU: Stop AMD counters when called from vpmu_save_force() Boris Ostrovsky
2014-01-21 19:08 ` [PATCH v4 03/17] x86/VPMU: Minor VPMU cleanup Boris Ostrovsky
2014-01-24 14:28 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 04/17] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
2014-01-21 19:08 ` [PATCH v4 05/17] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
2014-01-21 19:08 ` [PATCH v4 06/17] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero Boris Ostrovsky
2014-01-21 19:08 ` [PATCH v4 07/17] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2014-01-24 14:54 ` Jan Beulich
2014-01-24 16:49 ` Boris Ostrovsky
2014-01-24 16:57 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 08/17] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2014-01-24 14:59 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 09/17] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2014-01-24 15:10 ` Jan Beulich
2014-01-24 17:13 ` Boris Ostrovsky
2014-01-27 8:34 ` Jan Beulich
2014-01-27 15:20 ` Boris Ostrovsky
2014-01-27 15:29 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 10/17] x86/VPMU: Initialize PMU for PV guests Boris Ostrovsky
2014-01-31 16:58 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 11/17] x86/VPMU: Add support for PMU register handling on " Boris Ostrovsky
2014-02-04 11:14 ` Jan Beulich
2014-02-04 15:07 ` Boris Ostrovsky
2014-01-21 19:08 ` [PATCH v4 12/17] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
2014-02-04 11:22 ` Jan Beulich
2014-02-04 15:26 ` Boris Ostrovsky
2014-02-04 15:50 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 13/17] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2014-02-04 11:31 ` Jan Beulich
2014-02-04 15:53 ` Boris Ostrovsky
2014-02-04 16:01 ` Jan Beulich
2014-02-04 16:13 ` Boris Ostrovsky
2014-02-04 16:39 ` Jan Beulich
2014-01-21 19:08 ` [PATCH v4 14/17] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2014-02-04 11:38 ` Jan Beulich
2014-02-04 15:56 ` Boris Ostrovsky
2014-01-21 19:09 ` Boris Ostrovsky [this message]
2014-02-04 11:48 ` [PATCH v4 15/17] x86/VPMU: NMI-based VPMU support Jan Beulich
2014-02-04 16:31 ` Boris Ostrovsky
2014-02-04 16:41 ` Jan Beulich
2014-02-04 16:50 ` Boris Ostrovsky
2014-01-21 19:09 ` [PATCH v4 16/17] x86/VPMU: Suport for PVH guests Boris Ostrovsky
2014-02-04 11:51 ` Jan Beulich
2014-02-04 16:44 ` Boris Ostrovsky
2014-01-21 19:09 ` [PATCH v4 17/17] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
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