From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: JBeulich@suse.com
Cc: keir@xen.org, jun.nakajima@intel.com, andrew.cooper3@citrix.com,
eddie.dong@intel.com, dietmar.hahn@ts.fujitsu.com,
xen-devel@lists.xen.org, suravee.suthikulpanit@amd.com,
boris.ostrovsky@oracle.com
Subject: [PATCH v5 06/17] intel/VPMU: MSR_CORE_PERF_GLOBAL_CTRL should be initialized to zero
Date: Mon, 17 Feb 2014 12:55:53 -0500 [thread overview]
Message-ID: <1392659764-22183-7-git-send-email-boris.ostrovsky@oracle.com> (raw)
In-Reply-To: <1392659764-22183-1-git-send-email-boris.ostrovsky@oracle.com>
MSR_CORE_PERF_GLOBAL_CTRL register should be set zero initially. It is up to
the guest to set it so that counters are enabled.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
xen/arch/x86/hvm/vmx/vpmu_core2.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index c16ae10..c66289a 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -164,13 +164,6 @@ static int core2_get_fixed_pmc_count(void)
return ( (eax & PMU_FIXED_NR_MASK) >> PMU_FIXED_NR_SHIFT );
}
-static u64 core2_calc_intial_glb_ctrl_msr(void)
-{
- int arch_pmc_bits = (1 << arch_pmc_cnt) - 1;
- u64 fix_pmc_bits = (1 << fixed_pmc_cnt) - 1;
- return ( (fix_pmc_bits << 32) | arch_pmc_bits );
-}
-
/* edx bits 5-12: Bit width of fixed-function performance counters */
static int core2_get_bitwidth_fix_count(void)
{
@@ -373,8 +366,7 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
if ( vmx_add_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
goto out_err;
- vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL,
- core2_calc_intial_glb_ctrl_msr());
+ vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) +
(arch_pmc_cnt-1)*sizeof(struct arch_msr_pair));
--
1.8.1.4
next prev parent reply other threads:[~2014-02-17 17:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-17 17:55 [PATCH v5 00/17] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 01/17] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 02/17] VPMU: Mark context LOADED before registers are loaded Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 03/17] x86/VPMU: Minor VPMU cleanup Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 04/17] intel/VPMU: Clean up Intel VPMU code Boris Ostrovsky
2014-03-13 10:45 ` Dietmar Hahn
2014-02-17 17:55 ` [PATCH v5 05/17] x86/VPMU: Handle APIC_LVTPC accesses Boris Ostrovsky
2014-02-17 17:55 ` Boris Ostrovsky [this message]
2014-02-17 17:55 ` [PATCH v5 07/17] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 08/17] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 09/17] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 10/17] x86/VPMU: Initialize PMU for PV guests Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 11/17] x86/VPMU: Add support for PMU register handling on " Boris Ostrovsky
2014-02-17 17:55 ` [PATCH v5 12/17] x86/VPMU: Handle PMU interrupts for " Boris Ostrovsky
2014-02-17 17:56 ` [PATCH v5 13/17] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2014-02-17 17:56 ` [PATCH v5 14/17] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2014-02-17 17:56 ` [PATCH v5 15/17] x86/VPMU: NMI-based VPMU support Boris Ostrovsky
2014-02-17 17:56 ` [PATCH v5 16/17] x86/VPMU: Suport for PVH guests Boris Ostrovsky
2014-02-17 17:56 ` [PATCH v5 17/17] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2014-03-06 16:20 ` [PATCH v5 00/17] x86/PMU: Xen PMU PV(H) support Jan Beulich
2014-03-06 16:46 ` Boris Ostrovsky
2014-03-10 7:40 ` Dietmar Hahn
2014-03-13 10:47 ` Dietmar Hahn
2014-03-19 16:43 ` Boris Ostrovsky
2014-04-21 14:37 ` Konrad Rzeszutek Wilk
2014-04-22 23:48 ` Tian, Kevin
2014-04-23 12:50 ` Konrad Rzeszutek Wilk
2014-04-23 8:09 ` Tian, Kevin
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