From: Konrad Rzeszutek Wilk <konrad@kernel.org>
To: xen-devel@lists.xenproject.org, jbeulich@suse.com
Subject: [PATCH v1 4/4] serial: Expand the PCI serial quirks for OXPCIe200 and OXPCIe952 1 Native UART
Date: Wed, 5 Mar 2014 12:25:34 -0500 [thread overview]
Message-ID: <1394040334-16278-5-git-send-email-konrad.wilk@oracle.com> (raw)
In-Reply-To: <1394040334-16278-1-git-send-email-konrad.wilk@oracle.com>
This covers all of the OXPCIe952 1 Native UART and
OXPCIe200 1 Native UART chipsets.
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
xen/drivers/char/ns16550.c | 174 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 174 insertions(+), 0 deletions(-)
diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index 6fbf358..487bf7d 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -146,8 +146,182 @@ static struct ns16550_config_mmio __initdata uart_config[] =
/* OXPCIe952 1 Native UART */
{
.vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc11b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc11f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
.dev_id = 0xc138,
.quirk = quirk_oxford,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc13d,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc40b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc40f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc41b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc41f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc42b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc42f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc43b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc43f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc44b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc44f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc45b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc45f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc46b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc46f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc47b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc47f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc48b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc48f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc49b,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc49f,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4ab,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4af,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4bb,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4bf,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4cb,
+ .quirk = quirk_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4cf,
+ .quirk = quirk_oxford,
}
};
#endif
--
1.7.7.6
next prev parent reply other threads:[~2014-03-05 17:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-05 17:25 [PATCH v1] Enable serial output for Oxford Semiconductor PCIe cards Konrad Rzeszutek Wilk
2014-03-05 17:25 ` [PATCH v1 1/4] serial: Support OXPCIe952 aka Oxford Semiconductor Ltd Device c138 (1415:c138) Konrad Rzeszutek Wilk
2014-03-06 10:15 ` Jan Beulich
2014-03-06 18:47 ` Konrad Rzeszutek Wilk
2014-03-05 17:25 ` [PATCH v1 2/4] serial: Seperate the PCI device ids and quirks Konrad Rzeszutek Wilk
2014-03-06 10:17 ` Jan Beulich
2014-03-06 18:48 ` Konrad Rzeszutek Wilk
2014-03-05 17:25 ` [PATCH v1 3/4] serial: Use #defines for PCI vendor and models Konrad Rzeszutek Wilk
2014-03-05 17:34 ` Andrew Cooper
2014-03-06 10:18 ` Jan Beulich
2014-03-05 17:25 ` Konrad Rzeszutek Wilk [this message]
2014-03-06 10:20 ` [PATCH v1 4/4] serial: Expand the PCI serial quirks for OXPCIe200 and OXPCIe952 1 Native UART Jan Beulich
2014-03-07 15:55 ` Konrad Rzeszutek Wilk
2014-03-07 16:30 ` Jan Beulich
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