From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH] xen/arm: debug-exynos4210: Remove early_uart_init Date: Tue, 22 Apr 2014 14:41:14 +0100 Message-ID: <1398174074-2799-1-git-send-email-julien.grall@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wcawq-0001hG-Ce for xen-devel@lists.xenproject.org; Tue, 22 Apr 2014 13:41:20 +0000 Received: by mail-ee0-f51.google.com with SMTP id c13so4660289eek.38 for ; Tue, 22 Apr 2014 06:41:18 -0700 (PDT) List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: ian.campbell@citrix.com, HyonYoung Choi , Julien Grall , tim@xen.org, stefano.stabellini@citrix.com, Meng Xu List-Id: xen-devel@lists.xenproject.org The function early_uart_init contains specific initialization for the Arndale Board 5250. Usually U-boot as already setup the UART correctly (ie. clock, baud rate...) so we don't have to do again. Futhermore, this code won't work on new platform such as the Arndale Octa. Signed-off-by: Julien Grall Cc: HyonYoung Choi Cc: Meng Xu --- xen/arch/arm/Rules.mk | 1 - xen/arch/arm/arm32/debug-exynos4210.inc | 32 ------------------------------- 2 files changed, 33 deletions(-) diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index c551afb..8d5624b 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -53,7 +53,6 @@ EARLY_UART_BASE_ADDRESS := 0x1c090000 endif ifeq ($(CONFIG_EARLY_PRINTK), exynos5250) EARLY_PRINTK_INC := exynos4210 -EARLY_PRINTK_INIT_UART := y EARLY_PRINTK_BAUD := 115200 EARLY_UART_BASE_ADDRESS := 0x12c20000 endif diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc b/xen/arch/arm/arm32/debug-exynos4210.inc index 39f2db3..752942d 100644 --- a/xen/arch/arm/arm32/debug-exynos4210.inc +++ b/xen/arch/arm/arm32/debug-exynos4210.inc @@ -18,38 +18,6 @@ #include -/* Exynos 5 UART initialization - * rb: register which contains the UART base address - * rc: scratch register 1 - * rd: scratch register 2 */ -.macro early_uart_init rb rc rd - /* init clock */ - ldr \rc, =0x10020000 - /* select MPLL (800MHz) source clock */ - ldr \rd, [\rc, #0x250] - and \rd, \rd, #(~(0xf<<8)) - orr \rd, \rd, #(0x6<<8) - str \rd, [\rc, #0x250] - /* ratio 800/(7+1) */ - ldr \rd, [\rc, #0x558] - and \rd, \rd, #(~(0xf<<8)) - orr \rd, \rd, #(0x7<<8) - str \rd, [\rc, #0x558] - - mov \rc, #(100000000 / EARLY_PRINTK_BAUD % 16) - str \rc, [\rb, #UFRACVAL] /* -> UFRACVAL (Baud divisor fraction) */ - mov \rc, #(100000000 / EARLY_PRINTK_BAUD / 16 - 1) - str \rc, [\rb, #UBRDIV] /* -> UBRDIV (Baud divisor integer) */ - mov \rc, #3 /* 8n1 */ - str \rc, [\rb, #ULCON] /* -> (Line control) */ - ldr \rc, =UCON_TX_IRQ /* TX IRQMODE */ - str \rc, [\rb, #UCON] /* -> (Control Register) */ - mov \rc, #0x0 - str \rc, [\rb, #UFCON] /* disable FIFO */ - mov \rc, #0x0 - str \rc, [\rb, #UMCON] /* no auto flow control */ -.endm - /* Exynos 5 UART wait UART to be ready to transmit * rb: register which contains the UART base address * rc: scratch register */ -- 1.7.10.4