From mboxrd@z Thu Jan 1 00:00:00 1970 From: Feng Wu Subject: [PATCH v5 01/10] x86: define macros CPUINFO_features and CPUINFO_FEATURE_OFFSET Date: Tue, 6 May 2014 18:06:39 +0800 Message-ID: <1399370799-5261-1-git-send-email-feng.wu@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: kevin.tian@intel.com, Feng Wu , JBeulich@suse.com, andrew.cooper3@citrix.com, eddie.dong@intel.com, jun.nakajima@intel.com, ian.campbell@citrix.com List-Id: xen-devel@lists.xenproject.org This patch defines macros CPUINFO_features and CPUINFO_FEATURE_OFFSET. CPUINFO_features can be used as the base of the offset for cpu features, while CPUINFO_FEATURE_OFFSET is used to define the right offset for specific CPU feature. Signed-off-by: Feng Wu --- xen/arch/x86/boot/head.S | 3 ++- xen/arch/x86/x86_64/asm-offsets.c | 2 +- xen/include/asm-x86/asm_defns.h | 3 +++ xen/include/asm-x86/cpufeature.h | 4 ++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S index ca0e97d..8e4e065 100644 --- a/xen/arch/x86/boot/head.S +++ b/xen/arch/x86/boot/head.S @@ -6,6 +6,7 @@ #include #include #include +#include .text .code32 @@ -137,7 +138,7 @@ __start: mov $0x80000001,%eax cpuid 1: mov %edx,sym_phys(cpuid_ext_features) - mov %edx,sym_phys(boot_cpu_data)+CPUINFO86_ext_features + mov %edx,sym_phys(boot_cpu_data)+CPUINFO_FEATURE_OFFSET(X86_FEATURE_LM) /* Check for availability of long mode. */ bt $29,%edx diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c index 9acb648..5f46969 100644 --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -160,7 +160,7 @@ void __dummy__(void) OFFSET(IRQSTAT_softirq_pending, irq_cpustat_t, __softirq_pending); BLANK(); - OFFSET(CPUINFO86_ext_features, struct cpuinfo_x86, x86_capability[1]); + OFFSET(CPUINFO_features, struct cpuinfo_x86, x86_capability[0]); BLANK(); OFFSET(MB_flags, multiboot_info_t, flags); diff --git a/xen/include/asm-x86/asm_defns.h b/xen/include/asm-x86/asm_defns.h index a4601ba..2b055f5 100644 --- a/xen/include/asm-x86/asm_defns.h +++ b/xen/include/asm-x86/asm_defns.h @@ -77,6 +77,9 @@ void ret_from_intr(void); #define ASSERT_NOT_IN_ATOMIC #endif +#define CPUINFO_FEATURE_OFFSET(feature) \ + (((feature >> 3) & ~3) + CPUINFO_features) + #else #ifdef __clang__ /* clang's builtin assember can't do .subsection */ diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 6a6b1ab..20881c0 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -7,7 +7,9 @@ #ifndef __ASM_I386_CPUFEATURE_H #define __ASM_I386_CPUFEATURE_H +#ifndef __ASSEMBLY__ #include +#endif #define NCAPINTS 8 /* N 32-bit words worth of info */ @@ -152,6 +154,7 @@ #define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ +#ifndef __ASSEMBLY__ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) #define cpufeat_mask(idx) (1u << ((idx) & 31)) @@ -210,6 +213,7 @@ #define cpu_has_vmx boot_cpu_has(X86_FEATURE_VMXE) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) +#endif #endif /* __ASM_I386_CPUFEATURE_H */ -- 1.8.3.1