From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Stabellini Subject: [PATCH v2 1/2] xen/arm: ignore guest writes to GICD_ITARGETSR for SPIs Date: Tue, 3 Jun 2014 17:07:06 +0100 Message-ID: <1401811627-4389-1-git-send-email-stefano.stabellini@eu.citrix.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xensource.com Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini List-Id: xen-devel@lists.xenproject.org Ignore guest writes to GICD_ITARGETSR that set the target cpu to a cpu other than cpu0 for SPIs. Also ignore guest writes to GICD_ITARGETSR for PPIs and SGIs as they can only be delivered to the same cpu and that has already been configured at initialization time. Signed-off-by: Stefano Stabellini --- Changes in v2: - ignore writes to rank 0; - don't print a warning for ignoring writes to GICD_ITARGETSR; - add a comment in the code to remember that we don't implement writes to GICD_ITARGETSR. --- xen/arch/arm/vgic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index cb8df3a..1304b5e 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -584,6 +584,13 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info) if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width; rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR); if ( rank == NULL) goto write_ignore; + /* only same vcpu delivery can be allowed for PPIs and SGIs */ + if ( REG_RANK_NR(8, gicd_reg - GICD_ITARGETSR) == 0 ) + return 1; + /* SPI delivery to secondary vcpus is unimplemented */ + if ( REG_RANK_NR(8, gicd_reg - GICD_ITARGETSR) > 0 && + *r != (1|1<<8|1<<16|1<<24) ) + return 1; vgic_lock_rank(v, rank); if ( dabt.size == 2 ) rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r; -- 1.7.10.4