From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: [PATCH 5/5] xen: arm: flush TLB after overwriting 1:1 mapping in boot page tables Date: Mon, 14 Jul 2014 17:39:10 +0100 Message-ID: <1405355950-6461-5-git-send-email-ian.campbell@citrix.com> References: <1405355930.31863.5.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1405355930.31863.5.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Otherwise a stale TLB entry can shadow the fixmap/UART or DTB mapping Signed-off-by: Ian Campbell --- xen/arch/arm/arm32/head.S | 13 ++++++++++++- xen/arch/arm/arm64/head.S | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 348ca7d..a36c8fc 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -398,9 +398,20 @@ paging: ldr r4, =BOOT_FDT_VIRT_START mov r4, r4, lsr #(SECOND_SHIFT - 3) /* Slot for BOOT_FDT_VIRT_START */ strd r2, r3, [r1, r4] /* Map it in the early fdt slot */ - dsb 1: + /* + * Flush the TLB in case the 1:1 mapping happens to clash with + * the virtual addresses used by the fixmap or DTB. + */ + dsb /* Ensure any page table updates made above + * have occurred. */ + + isb + mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ + dsb /* Ensure completion of TLB flush */ + isb + PRINT("- Ready -\r\n") /* The boot CPU should go straight into C now */ diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 7152d9c..a50192e 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -432,9 +432,20 @@ paging: ldr x1, =BOOT_FDT_VIRT_START lsr x1, x1, #(SECOND_SHIFT - 3) /* x4 := Slot for BOOT_FDT_VIRT_START */ str x2, [x4, x1] /* Map it in the early fdt slot */ - dsb sy 1: + /* + * Flush the TLB in case the 1:1 mapping happens to clash with + * the virtual addresses used by the fixmap or DTB. + */ + dsb sy /* Ensure any page table updates made above + * have occurred. */ + + isb + tlbi alle2 + dsb sy /* Ensure completion of TLB flush */ + isb + PRINT("- Ready -\r\n") /* The boot CPU should go straight into C now */ -- 1.7.10.4