Re: [PATCH v8 03/10] xen/arm: inflight irqs during migration

[Ian Campbell <Ian.Campbell@citrix.com>]

On Thu, 2014-07-24 at 17:49 +0100, Stefano Stabellini wrote:
> On Thu, 24 Jul 2014, Ian Campbell wrote:
> > On Thu, 2014-07-24 at 17:45 +0100, Stefano Stabellini wrote:
> > > > Are you sure about the second physical IRQ always hitting on the source
> > > > pCPU though? I'm unclear about where the physical ITARGETSR gets written
> > > > in the scheme you are proposing.
> > > 
> > > It gets written right away if there are no inflight irqs.
> > 
> > There's no way that something can be pending in the physical GIC at this
> > point? i.e. because it happened since we took the trap?
> 
> If it is pending is OK: ARM ARM states that writes to itarget affect
> pending irqs too. Only active irqs are not affected. But we deal with
> that case separately.

So at the point where we write itarget the pending IRQ can potentially
be injected onto the new pCPU immediately, since it won't have it's IRQs
disabled etc.

Does our locking cope with that case?

Also the pending we are talking about here is in the physical
distributor, right? Not the various software state bits which we track.

So an IRQ which we have in lr_pending is actually active in the real
distributor (since we must have taken the interrupt to get it onto our
lists). I'm not sure how/if that changes your reasoning about these
things.

Ian.