From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mukesh Rathor Subject: [V0 PATCH 5/6] AMD-PVH: Support TSC_MODE_NEVER_EMULATE for PVH Date: Fri, 15 Aug 2014 18:53:15 -0700 Message-ID: <1408153996-16425-6-git-send-email-mukesh.rathor@oracle.com> References: <1408153996-16425-1-git-send-email-mukesh.rathor@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XITBZ-0007IO-Un for xen-devel@lists.xenproject.org; Sat, 16 Aug 2014 01:53:38 +0000 In-Reply-To: <1408153996-16425-1-git-send-email-mukesh.rathor@oracle.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: keir@xen.org, boris.ostrovsky@oracle.com, Aravind.Gopalakrishnan@amd.com, jbeulich@suse.com, suravee.suthikulpanit@amd.com List-Id: xen-devel@lists.xenproject.org On AMD, MSR_AMD64_TSC_RATIO must be set for rdtsc instruction in guest to properly read the cpu tsc. To that end, set tsc_khz in struct domain. Signed-off-by: Mukesh Rathor --- xen/arch/x86/time.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index bd89219..7512aa4 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1908,6 +1908,7 @@ void tsc_set_info(struct domain *d, * but "always_emulate" does not for some reason. Figure out * why. */ + d->arch.tsc_khz = cpu_khz; switch ( tsc_mode ) { case TSC_MODE_NEVER_EMULATE: -- 1.8.3.1