From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tamas K Lengyel Subject: [PATCH v4 12/16] xen/arm: Instruction prefetch abort (X) mem_event handling Date: Fri, 5 Sep 2014 10:58:40 +0200 Message-ID: <1409907524-12509-13-git-send-email-tklengyel@sec.in.tum.de> References: <1409907524-12509-1-git-send-email-tklengyel@sec.in.tum.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1409907524-12509-1-git-send-email-tklengyel@sec.in.tum.de> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, tim@xen.org, julien.grall@linaro.org, ian.jackson@eu.citrix.com, stefano.stabellini@citrix.com, andres@lagarcavilla.org, jbeulich@suse.com, dgdegra@tycho.nsa.gov, Tamas K Lengyel List-Id: xen-devel@lists.xenproject.org Add missing structure definition for iabt and update the trap handling mechanism to only inject the exception if the mem_access checker decides to do so. Signed-off-by: Tamas K Lengyel --- v4: - Don't mark instruction fetch violation as read violation. - Use new struct npfec to pass violation info. v2: - Add definition for instruction abort instruction fetch status codes (enum iabt_ifsc) and only call p2m_mem_access_check for traps triggered for permission violations. --- xen/arch/arm/traps.c | 42 ++++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/processor.h | 40 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 80 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 7eb875a..6f851cc 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1828,7 +1828,47 @@ done: static void do_trap_instr_abort_guest(struct cpu_user_regs *regs, union hsr hsr) { - register_t addr = READ_SYSREG(FAR_EL2); + struct hsr_iabt iabt = hsr.iabt; + int rc; + register_t addr; + vaddr_t gva; + paddr_t gpa; + +#ifdef CONFIG_ARM_32 + gva = READ_CP32(HIFAR); +#else + gva = READ_SYSREG64(FAR_EL2); +#endif + + rc = gva_to_ipa(gva, &gpa); + if ( rc == -EFAULT ) + return; + + switch ( iabt.ifsc ) + { + case IABT_IFSC_PERMISSION_1: + case IABT_IFSC_PERMISSION_2: + case IABT_IFSC_PERMISSION_3: + { + struct npfec npfec = { + .insn_fetch = 1, + .gla_valid = 1, + .kind = iabt.s1ptw ? npfec_kind_in_gpt : npfec_kind_with_gla + }; + + rc = p2m_mem_access_check(gpa, gva, npfec); + + /* Trap was triggered by mem_access, work here is done */ + if ( !rc ) + return; + } + break; + + default: + break; + } + + addr = READ_SYSREG(FAR_EL2); inject_iabt_exception(regs, addr, hsr.len); } diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b844f1d..044de12 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -292,6 +292,36 @@ enum dabt_dfsc { DABT_DFSC_TLB_CONFLICT = 0b110000, }; +/* Instruction abort instruction fault status codes */ +enum iabt_ifsc { + IABT_IFSC_ADDR_SIZE_0 = 0b000000, + IABT_IFSC_ADDR_SIZE_1 = 0b000001, + IABT_IFSC_ADDR_SIZE_2 = 0b000010, + IABT_IFSC_ADDR_SIZE_3 = 0b000011, + IABT_IFSC_TRANSLATION_0 = 0b000100, + IABT_IFSC_TRANSLATION_1 = 0b000101, + IABT_IFSC_TRANSLATION_2 = 0b000110, + IABT_IFSC_TRANSLATION_3 = 0b000111, + IABT_IFSC_ACCESS_1 = 0b001001, + IABT_IFSC_ACCESS_2 = 0b001010, + IABT_IFSC_ACCESS_3 = 0b001011, + IABT_IFSC_PERMISSION_1 = 0b001101, + IABT_IFSC_PERMISSION_2 = 0b001110, + IABT_IFSC_PERMISSION_3 = 0b001111, + IABT_IFSC_SYNC_EXT = 0b010000, + IABT_IFSC_SYNC_PARITY = 0b011000, + IABT_IFSC_SYNC_EXT_TTW_0 = 0b010100, + IABT_IFSC_SYNC_EXT_TTW_1 = 0b010101, + IABT_IFSC_SYNC_EXT_TTW_2 = 0b010110, + IABT_IFSC_SYNC_EXT_TTW_3 = 0b010111, + IABT_IFSC_SYNC_PARITY_TTW_0 = 0b011100, + IABT_IFSC_SYNC_PARITY_TTW_1 = 0b011101, + IABT_IFSC_SYNC_PARITY_TTW_2 = 0b011110, + IABT_IFSC_SYNC_PARITY_TTW_3 = 0b011111, + IABT_IFSC_ALIGNMENT = 0b100001, + IABT_IFSC_TLB_CONFLICT = 0b110000, +}; + union hsr { uint32_t bits; struct { @@ -371,10 +401,18 @@ union hsr { } sysreg; /* HSR_EC_SYSREG */ #endif + struct hsr_iabt { + unsigned long ifsc:6; /* Instruction fault status code */ + unsigned long res0:1; + unsigned long s1ptw:1; /* Fault during a stage 1 translation table walk */ + unsigned long res1:1; + unsigned long ea:1; /* External abort type */ + } iabt; /* HSR_EC_INSTR_ABORT_* */ + struct hsr_dabt { unsigned long dfsc:6; /* Data Fault Status Code */ unsigned long write:1; /* Write / not Read */ - unsigned long s1ptw:1; /* */ + unsigned long s1ptw:1; /* Fault during a stage 1 translation table walk */ unsigned long cache:1; /* Cache Maintenance */ unsigned long eat:1; /* External Abort Type */ #ifdef CONFIG_ARM_32 -- 2.1.0