From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: [PATCH 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap Date: Tue, 9 Sep 2014 17:23:02 +0100 Message-ID: <1410279788-27167-3-git-send-email-ian.campbell@citrix.com> References: <1410279730.8217.238.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1410279730.8217.238.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Signed-off-by: Ian Campbell --- xen/arch/arm/traps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1b1d29f..353e38e 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1370,7 +1370,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr) { unsigned long it; - BUG_ON( !is_32bit_domain(current->domain) || !(cpsr&PSR_THUMB) ); + BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) ); it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 ); @@ -1379,7 +1379,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr) return 1; /* The cond for this instruction works out as the top 4 bits. */ - cond = ( it >> 4 ); + cond = ( it >> 4 ); } cpsr_cond = cpsr >> 28; @@ -1395,10 +1395,10 @@ static void advance_pc(struct cpu_user_regs *regs, union hsr hsr) unsigned long itbits, cond, cpsr = regs->cpsr; /* PSR_IT_MASK bits can only be set for 32-bit processors in Thumb mode. */ - BUG_ON( (!is_32bit_domain(current->domain)||!(cpsr&PSR_THUMB)) + BUG_ON( (!psr_mode_is_32bit(cpsr)||!(cpsr&PSR_THUMB)) && (cpsr&PSR_IT_MASK) ); - if ( is_32bit_domain(current->domain) && (cpsr&PSR_IT_MASK) ) + if ( cpsr&PSR_IT_MASK ) { /* The ITSTATE[7:0] block is contained in CPSR[15:10],CPSR[26:25] * -- 1.7.10.4