From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: Panic on Seattle (resend) Date: Tue, 30 Sep 2014 11:45:03 +0100 Message-ID: <1412073903.25650.7.camel@citrix.com> References: <542A5F07.2030600@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <542A5F07.2030600@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Suravee Suthikulpanit Cc: Julien Grall , xen-devel , "stefano.stabellini@eu.citrix.com" List-Id: xen-devel@lists.xenproject.org On Tue, 2014-09-30 at 02:43 -0500, Suravee Suthikulpanit wrote: > Hi All, > > I have been trying to boot the latest Xen code on Seattle (while I am > getting the patch ready to be sent out), and I ran into the following issue. > > ..... > (XEN) Brought up 6 CPUs > (XEN) CPU 5 booted. > (XEN) P2M: 44-bit IPA with 44-bit PA > (XEN) P2M: 4 levels with order-0 root, VTCR 0x80043594 > (XEN) *** LOADING DOMAIN 0 *** > (XEN) Loading kernel from boot module @ 0000008008800000 > (XEN) elf_init: not an ELF binary > (XEN) > (XEN) **************************************** > (XEN) Panic on CPU 0: > (XEN) Could not set up DOM0 guest OS > (XEN) **************************************** > (XEN) > (XEN) Manual reset required ('noreboot' specified) > > I have not tracked down to a particular commit ID. But do you guys see > anything suspicious with the error message? The elf_init thing is suspicious, it suggests Xen hasn't properly figured out the type of your kernel image. Is it a regular bare arm64 Image (from arch/arm64/boot/Image)? You can't boot the vmlinux from the top level directly (AFAIK). > My understanding is with 4-level page, it requires 4K page and 48 bits > PA. However, the message above showing 44-bit PA. Is this intentional? The 44 comes from ID_AA64MMFR0_EL1.PARange. 4-levels are required for anything above 40-bits, so 44-bit PA also needs 4-levels. This comes from things like tables D4-5 and D4-10 in the ARMv8 ARM, which give the T0SZ range and maximum number of levels/concatenation for various PAsizes. Ian.