From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH 1/4] xen/arm: introduce invalidate_xen_dcache_va_range Date: Fri, 3 Oct 2014 15:00:19 +0100 Message-ID: <1412344819.12695.19.camel@citrix.com> References: <1412244158-12124-1-git-send-email-stefano.stabellini@eu.citrix.com> <542D3D93.6000607@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <542D3D93.6000607@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: xen-devel@lists.xensource.com, Stefano Stabellini List-Id: xen-devel@lists.xenproject.org On Thu, 2014-10-02 at 12:57 +0100, Julien Grall wrote: > Hi Stefano, > > n 10/02/2014 11:02 AM, Stefano Stabellini wrote: > > + > > +static inline void invalidate_xen_dcache_va_range(const void *p, unsigned long size) > > +{ > > + size_t off; > > + const void *end = p + size; > > + > > + dsb(sy); /* So the CPU issues all writes to the range */ > > I'm wondering if we could relax the dsb(sy) to dsb(ish)? We would need to know which cache level the device we are talking to is coherent with, which we don't know so we have to be conservative. Also since you only need this hypercall for incoherent devices I suppose it needs to push things all the way down. Ian.