From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: JBeulich@suse.com, kevin.tian@intel.com,
suravee.suthikulpanit@amd.com, Aravind.Gopalakrishnan@amd.com,
dietmar.hahn@ts.fujitsu.com, dgdegra@tycho.nsa.gov,
andrew.cooper3@citrix.com, jun.nakajima@intel.com, tim@xen.org,
xen-devel@lists.xen.org
Cc: boris.ostrovsky@oracle.com
Subject: [PATCH v23 10/15] x86/VPMU: Use pre-computed masks when checking validity of MSRs
Date: Fri, 29 May 2015 14:42:55 -0400 [thread overview]
Message-ID: <1432924980-24281-11-git-send-email-boris.ostrovsky@oracle.com> (raw)
In-Reply-To: <1432924980-24281-1-git-send-email-boris.ostrovsky@oracle.com>
No need to compute those masks on every MSR access.
Also, when checking MSR_P6_EVNTSELx registers make sure that bit 21
is not set.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
Changes in v23:
* Mention new test for bit MSR_P6_EVNTSELx[21] in commit message
xen/arch/x86/hvm/vmx/vpmu_core2.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index e5478a1..e8d9bb4 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -80,9 +80,16 @@ static bool_t __read_mostly full_width_write;
#define FIXED_CTR_CTRL_BITS 4
#define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
+#define ARCH_CNTR_ENABLED (1ULL << 22)
+
/* Number of general-purpose and fixed performance counters */
static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt;
+/* Masks used for testing whether and MSR is valid */
+#define ARCH_CTRL_MASK (~((1ull << 32) - 1) | (1ull << 21))
+static uint64_t __read_mostly fixed_ctrl_mask, fixed_counters_mask;
+static uint64_t __read_mostly global_ovf_ctrl_mask;
+
/*
* QUIRK to workaround an issue on various family 6 cpus.
* The issue leads to endless PMC interrupt loops on the processor.
@@ -479,9 +486,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
ASSERT(!supported);
- if ( type == MSR_TYPE_COUNTER &&
- (msr_content &
- ~((1ull << core2_get_bitwidth_fix_count()) - 1)) )
+ if ( (type == MSR_TYPE_COUNTER) && (msr_content & fixed_counters_mask) )
/* Writing unsupported bits to a fixed counter */
return 1;
@@ -490,9 +495,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
switch ( msr )
{
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
- if ( msr_content & ~(0xC000000000000000 |
- (((1ULL << fixed_pmc_cnt) - 1) << 32) |
- ((1ULL << arch_pmc_cnt) - 1)) )
+ if ( msr_content & global_ovf_ctrl_mask )
return 1;
core2_vpmu_cxt->global_status &= ~msr_content;
wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
@@ -526,8 +529,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
core2_vpmu_cxt->global_ctrl = msr_content;
break;
case MSR_CORE_PERF_FIXED_CTR_CTRL:
- if ( msr_content &
- ( ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1)) )
+ if ( msr_content & fixed_ctrl_mask )
return 1;
if ( has_hvm_container_vcpu(v) )
@@ -556,7 +558,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
struct xen_pmu_cntr_pair *xen_pmu_cntr_pair =
vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
- if ( msr_content & (~((1ull << 32) - 1)) )
+ if ( msr_content & ARCH_CTRL_MASK )
return 1;
if ( has_hvm_container_vcpu(v) )
@@ -565,7 +567,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
else
rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl);
- if ( msr_content & (1ULL << 22) )
+ if ( msr_content & ARCH_CNTR_ENABLED )
*enabled_cntrs |= 1ULL << tmp;
else
*enabled_cntrs &= ~(1ULL << tmp);
@@ -915,6 +917,12 @@ int __init core2_vpmu_init(void)
rdmsrl(MSR_IA32_PERF_CAPABILITIES, caps);
full_width_write = (caps >> 13) & 1;
+ fixed_ctrl_mask = ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1);
+ fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1);
+ global_ovf_ctrl_mask = ~(0xC000000000000000 |
+ (((1ULL << fixed_pmc_cnt) - 1) << 32) |
+ ((1ULL << arch_pmc_cnt) - 1));
+
check_pmc_quirk();
if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt +
--
1.8.1.4
next prev parent reply other threads:[~2015-05-29 18:42 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-29 18:42 [PATCH v23 00/15] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 01/15] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 02/15] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 03/15] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 04/15] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 05/15] x86/VPMU: Initialize VPMUs with __initcall Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 06/15] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 07/15] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 08/15] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 09/15] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
2015-05-29 18:42 ` Boris Ostrovsky [this message]
2015-06-01 11:07 ` [PATCH v23 10/15] x86/VPMU: Use pre-computed masks when checking validity of MSRs Jan Beulich
2015-05-29 18:42 ` [PATCH v23 11/15] VPMU/AMD: Check MSR values before writing to hardware Boris Ostrovsky
2015-06-05 16:03 ` Jan Beulich
2015-06-05 16:32 ` Boris Ostrovsky
2015-06-08 9:22 ` Jan Beulich
2015-05-29 18:42 ` [PATCH v23 12/15] x86/VPMU: Handle PMU interrupts for PV(H) guests Boris Ostrovsky
2015-06-05 16:09 ` Jan Beulich
2015-06-05 16:38 ` Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 13/15] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
2015-05-29 18:42 ` [PATCH v23 14/15] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2015-05-29 18:43 ` [PATCH v23 15/15] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
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