From: Chao Peng <chao.p.peng@linux.intel.com>
To: xen-devel@lists.xen.org
Cc: keir@xen.org, Ian.Campbell@citrix.com,
stefano.stabellini@eu.citrix.com, andrew.cooper3@citrix.com,
dario.faggioli@citrix.com, Ian.Jackson@eu.citrix.com,
will.auld@intel.com, JBeulich@suse.com, wei.liu2@citrix.com,
dgdegra@tycho.nsa.gov
Subject: [PATCH v9 07/13] x86: add scheduling support for Intel CAT
Date: Wed, 3 Jun 2015 12:53:04 +0800 [thread overview]
Message-ID: <1433307190-6381-8-git-send-email-chao.p.peng@linux.intel.com> (raw)
In-Reply-To: <1433307190-6381-1-git-send-email-chao.p.peng@linux.intel.com>
On context switch, write the the domain's Class of Service(COS) to MSR
IA32_PQR_ASSOC, to notify hardware to use the new COS.
For performance reason, the COS mask for current cpu is also cached in
the local per-CPU variable.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
Changes in v5:
* Remove the need to cache socket.
Changes in v2:
* merge common scheduling changes into scheduling improvement patch.
* use readable expr for psra->cos_mask.
---
xen/arch/x86/psr.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index fce5bca..daa3c9c 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -35,6 +35,7 @@ struct psr_cat_socket_info {
struct psr_assoc {
uint64_t val;
+ uint64_t cos_mask;
};
struct psr_cmt *__read_mostly psr_cmt;
@@ -200,7 +201,16 @@ static inline void psr_assoc_init(void)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
- if ( psr_cmt_enabled() )
+ if ( cat_socket_info )
+ {
+ unsigned int socket = cpu_to_socket(smp_processor_id());
+
+ if ( test_bit(socket, cat_socket_enable) )
+ psra->cos_mask = ((1ull << get_count_order(
+ cat_socket_info[socket].cos_max)) - 1) << 32;
+ }
+
+ if ( psr_cmt_enabled() || psra->cos_mask )
rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
}
@@ -209,6 +219,12 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned int rmid)
*reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
}
+static inline void psr_assoc_cos(uint64_t *reg, unsigned int cos,
+ uint64_t cos_mask)
+{
+ *reg = (*reg & ~cos_mask) | (((uint64_t)cos << 32) & cos_mask);
+}
+
void psr_ctxt_switch_to(struct domain *d)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
@@ -217,6 +233,11 @@ void psr_ctxt_switch_to(struct domain *d)
if ( psr_cmt_enabled() )
psr_assoc_rmid(®, d->arch.psr_rmid);
+ if ( psra->cos_mask )
+ psr_assoc_cos(®, d->arch.psr_cos_ids ?
+ d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
+ 0, psra->cos_mask);
+
if ( reg != psra->val )
{
wrmsrl(MSR_IA32_PSR_ASSOC, reg);
--
1.9.1
next prev parent reply other threads:[~2015-06-03 4:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 4:52 [PATCH v9 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
2015-06-03 4:52 ` [PATCH v9 01/13] x86: add socket_cpumask Chao Peng
2015-06-15 15:59 ` Jan Beulich
2015-06-03 4:52 ` [PATCH v9 02/13] x86: detect and initialize Intel CAT feature Chao Peng
2015-06-15 15:56 ` Jan Beulich
2015-06-03 4:53 ` [PATCH v9 03/13] x86: maintain COS to CBM mapping for each socket Chao Peng
2015-06-15 16:02 ` Jan Beulich
2015-06-23 7:08 ` Chao Peng
2015-06-23 8:27 ` Jan Beulich
2015-06-03 4:53 ` [PATCH v9 04/13] x86: add COS information for each domain Chao Peng
2015-06-16 6:55 ` Jan Beulich
2015-06-03 4:53 ` [PATCH v9 05/13] x86: expose CBM length and COS number information Chao Peng
2015-06-16 6:58 ` Jan Beulich
2015-06-03 4:53 ` [PATCH v9 06/13] x86: dynamically get/set CBM for a domain Chao Peng
2015-06-16 7:08 ` Jan Beulich
2015-06-23 7:19 ` Chao Peng
2015-06-23 8:35 ` Jan Beulich
2015-06-23 9:03 ` Chao Peng
2015-06-23 9:14 ` Jan Beulich
2015-06-03 4:53 ` Chao Peng [this message]
2015-06-03 4:53 ` [PATCH v9 08/13] xsm: add CAT related xsm policies Chao Peng
2015-06-03 4:53 ` [PATCH v9 09/13] tools/libxl: minor name changes for CMT commands Chao Peng
2015-06-03 4:53 ` [PATCH v9 10/13] tools/libxl: add command to show PSR hardware info Chao Peng
2015-06-03 4:53 ` [PATCH v9 11/13] tools/libxl: introduce some socket helpers Chao Peng
2015-06-03 4:53 ` [PATCH v9 12/13] tools: add tools support for Intel CAT Chao Peng
2015-06-03 4:53 ` [PATCH v9 13/13] docs: add xl-psr.markdown Chao Peng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1433307190-6381-8-git-send-email-chao.p.peng@linux.intel.com \
--to=chao.p.peng@linux.intel.com \
--cc=Ian.Campbell@citrix.com \
--cc=Ian.Jackson@eu.citrix.com \
--cc=JBeulich@suse.com \
--cc=andrew.cooper3@citrix.com \
--cc=dario.faggioli@citrix.com \
--cc=dgdegra@tycho.nsa.gov \
--cc=keir@xen.org \
--cc=stefano.stabellini@eu.citrix.com \
--cc=wei.liu2@citrix.com \
--cc=will.auld@intel.com \
--cc=xen-devel@lists.xen.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).