From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: Requesting for freeze exception for ARM/ITS patches Date: Sat, 11 Jul 2015 10:21:04 +0100 Message-ID: <1436606464.7019.4.camel@citrix.com> References: <1436544449.10074.120.camel@citrix.com> <55A0C352.9050100@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55A0C352.9050100@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: Wei Liu , Vijay Kilari , Stefano Stabellini , Prasun Kapoor , manish.jaggi@caviumnetworks.com, "xen-devel@lists.xen.org" , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org On Sat, 2015-07-11 at 09:18 +0200, Julien Grall wrote: > > As I explained in my reply to Jan I think this is underselling it a > > little, since AIUI it should make it possible to boot Xen on ThunderX > > and do useful things (like run guests). > > Well, PCI are able to support both legacy interrupt and MSI. If there is > no MSI, the PCI will use the former. The performance may be "poor" but > it will at least boot Xen on ThunderX and creating guest. AIUI ThunderX's on-SoC PCI devices do not provide legacy PCI INTX interrupts, only MSI/LPI interrupts. Perhaps someone from Cavium can confirm whether or not this is the case. Ian.