[PATCH v6 10/31] xen/arm: ITS: Introduce gic_is_lpi helper function

[vijay.kilari@gmail.com]

From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>

Helper function gic_is_lpi() is used to find
if irq is lpi or not. For GICv2 platforms this function
returns number of IRQ id bits which holds only number of line irqs.
For GICv3 platform it read id_bits from GICD_TYPER

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
CC: Zoltan Kiss <zoltan.kiss@huawei.com>
---
v6: - Added gic_info.nr_id_bits to hold number of SPI/LPIs
      supported
    - Dropped is_lpi() callback
---
 xen/arch/arm/gic-hip04.c          |    3 ++-
 xen/arch/arm/gic-v2.c             |    3 ++-
 xen/arch/arm/gic-v3.c             |    6 ++++++
 xen/arch/arm/gic.c                |    9 +++++++++
 xen/include/asm-arm/gic.h         |    4 ++++
 xen/include/asm-arm/gic_v3_defs.h |    3 ++-
 6 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c
index c5ed545..b5811e6 100644
--- a/xen/arch/arm/gic-hip04.c
+++ b/xen/arch/arm/gic-hip04.c
@@ -301,7 +301,8 @@ static void __init hip04gic_dist_init(void)
 
     /* Only 1020 interrupts are supported */
     gicv2_info.nr_lines = min(1020U, nr_lines);
-
+    /* Number of IRQ ids supported */
+    gicv2_info.nr_id_bits = get_count_order(gicv2_info.nr_lines);
     /* Turn on the distributor */
     writel_gicd(GICD_CTL_ENABLE, GICD_CTLR);
 }
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 596126d..364343d 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -291,7 +291,8 @@ static void __init gicv2_dist_init(void)
 
     /* Only 1020 interrupts are supported */
     gicv2_info.nr_lines = min(1020U, nr_lines);
-
+    /* Number of IRQ ids supported */
+    gicv2_info.nr_id_bits = get_count_order(gicv2_info.nr_lines);
     /* Turn on the distributor */
     writel_gicd(GICD_CTL_ENABLE, GICD_CTLR);
 }
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 5076706..e90e0cc 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -1270,6 +1270,12 @@ static int __init gicv3_init(void)
                      gicv3.rdist_stride);
     gicv3_init_v2(node, dbase);
 
+    reg = readl_relaxed(GICD + GICD_TYPER);
+
+    gicv3.rdist_data.id_bits = ((reg >> GICD_TYPE_ID_BITS_SHIFT) &
+                                GICD_TYPE_ID_BITS_MASK) + 1;
+    gicv3_info.nr_id_bits = gicv3.rdist_data.id_bits;
+
     spin_lock_init(&gicv3.lock);
 
     spin_lock(&gicv3.lock);
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 758678d..2199963 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -62,6 +62,15 @@ enum gic_version gic_hw_version(void)
    return gic_hw_ops->info->hw_version;
 }
 
+#ifdef HAS_GICV3
+bool_t gic_is_lpi(unsigned int irq)
+{
+    return (irq >= FIRST_GIC_LPI && irq < (1 << gic_hw_ops->info->nr_id_bits));
+}
+#else
+bool_t gic_is_lpi(unsigned int irq) { return 0; }
+#endif
+
 unsigned int gic_number_lines(void)
 {
     return gic_hw_ops->info->nr_lines;
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index e330fe3..d39e1b3 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -20,6 +20,7 @@
 
 #define NR_GIC_LOCAL_IRQS  NR_LOCAL_IRQS
 #define NR_GIC_SGI         16
+#define FIRST_GIC_LPI      8192
 #define MAX_RDIST_COUNT    4
 
 #define GICD_CTLR       (0x000)
@@ -299,6 +300,8 @@ struct gic_info {
     unsigned int maintenance_irq;
     /* Pointer to the device tree node representing the interrupt controller */
     const struct dt_device_node *node;
+    /* Number of IRQ ID bits supported */
+    uint32_t nr_id_bits;
 };
 
 struct gic_hw_operations {
@@ -359,6 +362,7 @@ void register_gic_ops(const struct gic_hw_operations *ops);
 int gic_make_hwdom_dt_node(const struct domain *d,
                            const struct dt_device_node *node,
                            void *fdt);
+bool_t gic_is_lpi(unsigned int irq);
 
 #endif /* __ASSEMBLY__ */
 #endif
diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
index 2c322da..1153509 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -46,7 +46,8 @@
 #define GICC_SRE_EL2_ENEL1           (1UL << 3)
 
 /* Additional bits in GICD_TYPER defined by GICv3 */
-#define GICD_TYPE_ID_BITS_SHIFT 19
+#define GICD_TYPE_ID_BITS_SHIFT      19
+#define GICD_TYPE_ID_BITS_MASK       0x1f
 
 #define GICD_TYPER_LPIS_SUPPORTED    (1U << 17)
 #define GICD_CTLR_RWP                (1UL << 31)
-- 
1.7.9.5