From: Ian Campbell <ian.campbell@citrix.com>
To: Jan Beulich <JBeulich@suse.com>,
Manish Jaggi <mjaggi@caviumnetworks.com>
Cc: "Prasun.kapoor@cavium.com" <Prasun.kapoor@cavium.com>,
Vijaya Kumar <Vijaya.Kumar@caviumnetworks.com>,
Julien Grall <julien.grall@linaro.org>,
Xen Devel <xen-devel@lists.xen.org>,
stefano.stabellini@eu.citrix.com
Subject: Re: PCI Pass-through in Xen ARM: Draft 4
Date: Wed, 2 Sep 2015 15:57:48 +0100 [thread overview]
Message-ID: <1441205868.26292.232.camel@citrix.com> (raw)
In-Reply-To: <55CCD3F1020000780009AC34@prv-mh.provo.novell.com>
On Thu, 2015-08-13 at 09:29 -0600, Jan Beulich wrote:
> >>> On 13.08.15 at 11:42, <mjaggi@caviumnetworks.com>
> wrote:
> > 2.1 pci_hostbridge and pci_hostbridge_ops
> > ---------------------------------------------------------------------
> > --------
> > The init function in the PCI host driver calls to register hostbridge
> > callbacks:
> >
> > int pci_hostbridge_register(pci_hostbridge_t *pcihb);
> >
> > struct pci_hostbridge_ops {
> > u32 (*pci_conf_read)(struct pci_hostbridge*, u32 bus, u32 devfn,
> > u32 reg, u32 bytes);
> > void (*pci_conf_write)(struct pci_hostbridge*, u32 bus, u32
> > devfn,
> > u32 reg, u32 bytes, u32 val);
> > };
> >
> > struct pci_hostbridge{
> > u32 segno;
> > paddr_t cfg_base;
> > paddr_t cfg_size;
> > struct dt_device_node *dt_node;
> > struct pci_hostbridge_ops ops;
> > struct list_head list;
> > };
> >
> > A PCI conf_read function would internally be as follows:
> > u32 pcihb_conf_read(u32 seg, u32 bus, u32 devfn,u32 reg, u32 bytes)
> > {
> > pci_hostbridge_t *pcihb;
> > list_for_each_entry(pcihb, &pci_hostbridge_list, list)
> > {
> > if(pcihb-segno == seg)
> > return pcihb-ops.pci_conf_read(pcihb, bus, devfn, reg,
> > bytes);
> > }
> > return -1;
> > }
>
> Which implies 1 segment per host bridge, which doesn't seem too
> nice to me: I can't see why a bridge might not cover more than one
> segment, and I also can't see why you shouldn't be able to put
> multiple bridges in the same segment when the number of busses
> they have is small.
Does this imply that:
#define PHYSDEVOP_pci_host_bridge_add <<>>
struct physdev_pci_host_bridge_add {
/* IN */
uint16_t seg;
uint64_t cfg_base;
uint64_t cfg_size;
};
(as specified in this draft 4) ought to have a bus field (as proposed in
http://article.gmane.org/gmane.comp.emulators.xen.devel/233386) or perhaps
even a bus and nr_buses field to give a span?
And then that the lookup functions ought to take those into account, of
course.
In the case where a single bridge covers multiple segments would we then
need to support calling this function multiple times i.e. once for each
segment the bridge contains each pointing to the same cfg region? Or
something similar.
Ian.
next prev parent reply other threads:[~2015-09-02 14:57 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-13 9:42 PCI Pass-through in Xen ARM: Draft 4 Manish Jaggi
2015-08-13 10:37 ` Julien Grall
2015-09-02 15:19 ` Ian Campbell
2015-09-02 15:40 ` Julien Grall
2015-08-13 15:29 ` Jan Beulich
2015-08-13 17:01 ` Ian Campbell
2015-08-14 9:26 ` Jan Beulich
2015-08-14 13:21 ` Stefano Stabellini
2015-08-14 13:58 ` Jan Beulich
2015-08-14 14:03 ` Stefano Stabellini
2015-08-14 14:34 ` Jan Beulich
2015-08-14 14:37 ` Stefano Stabellini
2015-08-14 14:45 ` Julien Grall
2015-08-14 15:15 ` Jan Beulich
2015-08-14 15:24 ` Stefano Stabellini
2015-09-02 14:45 ` Ian Campbell
2015-09-02 14:52 ` Jan Beulich
2015-09-02 15:07 ` Ian Campbell
2015-09-02 14:47 ` Ian Campbell
2015-08-14 15:38 ` Stefano Stabellini
2015-08-14 18:58 ` Jaggi, Manish
2015-08-16 23:59 ` Stefano Stabellini
2015-09-02 14:57 ` Ian Campbell [this message]
2015-09-02 15:06 ` Jan Beulich
2015-08-31 12:36 ` Manish Jaggi
2015-09-01 7:32 ` Jan Beulich
2015-09-02 12:08 ` Manish Jaggi
2015-09-02 12:59 ` Julien Grall
2015-09-02 13:46 ` Ian Campbell
2015-09-02 15:03 ` Ian Campbell
2015-09-02 15:03 ` Ian Campbell
2015-09-01 16:15 ` Stefano Stabellini
2015-09-10 1:12 ` Julien Grall
2015-09-15 18:58 ` Jaggi, Manish
2015-09-15 21:18 ` David Daney
2015-09-16 12:58 ` Julien Grall
2015-09-19 20:24 ` Manish Jaggi
2015-09-19 20:48 ` Julien Grall
2015-09-19 21:51 ` Daney, David
2015-09-21 10:17 ` Julien Grall
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