From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peng Fan Subject: [PATCH 2/2] xen: arm: traps: correct cond Date: Mon, 21 Sep 2015 15:07:56 +0800 Message-ID: <1442819276-25437-1-git-send-email-Peng.Fan@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: Julien Grall , Peng.Fan@freescale.com, Stefano Stabellini , Ian Campbell List-Id: xen-devel@lists.xenproject.org >>From "G6.2.29 CPSR, Current Program Status Register" of Aarch64 ARM and "B1.3.3 Program Status Registers (PSRs)" of ARMv7-A ARM: " IT[7:5] holds the base condition for the IT block. The base condition is the top 3 bits of the condition code specified by the first condition field of the IT instruction. IT[4:0] encodes the size of the IT block, which is the number of instructions that are to be conditionally executed, by the position of the least significant 1 in this field. It also encodes the value of the least significant bit of the condition code for each instruction in the block. " So should be "cond = ( it >> 5 );" but not "cond = ( it >> 4 );" Signed-off-by: Peng Fan Cc: Ian Campbell Cc: Stefano Stabellini Cc: Julien Grall --- xen/arch/arm/traps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 2e2b1f2..b2879b7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1561,8 +1561,8 @@ static int check_conditional_instr(struct cpu_user_regs *regs, if ( it == 0 ) return 1; - /* The cond for this instruction works out as the top 4 bits. */ - cond = ( it >> 4 ); + /* The cond for this instruction works out as the top 3 bits. */ + cond = ( it >> 5 ); } cpsr_cond = cpsr >> 28; -- 1.8.4