From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH for 4.6] xen/arm: vgic: Correctly emulate write when byte is used Date: Thu, 24 Sep 2015 12:30:25 +0100 Message-ID: <1443094225.10338.300.camel@citrix.com> References: <1442953128-4669-1-git-send-email-julien.grall@citrix.com> <20150923132358.GD9104@zion.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zf4jm-0005NF-0o for xen-devel@lists.xenproject.org; Thu, 24 Sep 2015 11:30:54 +0000 In-Reply-To: <20150923132358.GD9104@zion.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Wei Liu , Julien Grall Cc: xen-devel@lists.xenproject.org, stefano.stabellini@citrix.com List-Id: xen-devel@lists.xenproject.org On Wed, 2015-09-23 at 14:23 +0100, Wei Liu wrote: > On Tue, Sep 22, 2015 at 09:18:48PM +0100, Julien Grall wrote: > > When a guest is writing a byte, the value will be located in bits[7:0] > > of the register. > > > > Although the current implementation is expecting the byte at the Nth > > byte of the register where N = address & 4; > > > > When the address is not 4-byte aligned, the corresponding byte in the > > internal state will always be set to zero rather. > > > > Note that byte access are only used for GICD_IPRIORITYR and > > GICD_ITARGETSR. So the worst things that could happen is not setting > > the > > priority correctly and ignore the target vCPU written. > > > > Signed-off-by: Julien Grall > > > > Subject to an ack / review from ARM folks: > > Release-acked-by: Wei Liu Acked + applied to staging and staging-4.6, noted for later backport to 4.5 and 4.4.