From: Quan Xu <quan.xu@intel.com>
To: yang.z.zhang@intel.com, kevin.tian@intel.com, xen-devel@lists.xen.org
Cc: Quan Xu <quan.xu@intel.com>, jbeulich@suse.com
Subject: [PATCH] vt-d: Fix IM bit unmask of Fault Event Control Register in init_vtd_hw().
Date: Fri, 25 Sep 2015 15:22:35 +0800 [thread overview]
Message-ID: <1443165755-89680-1-git-send-email-quan.xu@intel.com> (raw)
Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved',
software cannot write 0 to it unconditionally. Software must preserve
the value read for writes.
Signed-off-by: Quan Xu <quan.xu@intel.com>
Reported-by: Jan Beulich <jbeulich@suse.com>
---
xen/drivers/passthrough/vtd/iommu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index f31d41b..bf9d6e8 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -2277,6 +2277,7 @@ static int init_vtd_hw(void)
struct iommu_flush *flush = NULL;
int ret;
unsigned long flags;
+ u32 sts;
/*
* Basic VT-d HW init: set VT-d interrupt, clear VT-d faults.
@@ -2290,7 +2291,9 @@ static int init_vtd_hw(void)
clear_fault_bits(iommu);
spin_lock_irqsave(&iommu->register_lock, flags);
- dmar_writel(iommu->reg, DMAR_FECTL_REG, 0);
+ sts = dmar_readl(iommu->reg, DMAR_FECTL_REG);
+ sts &= ~DMA_FECTL_IM;
+ dmar_writel(iommu->reg, DMAR_FECTL_REG, sts);
spin_unlock_irqrestore(&iommu->register_lock, flags);
}
--
1.8.3.2
next reply other threads:[~2015-09-25 7:22 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-25 7:22 Quan Xu [this message]
2015-09-25 18:57 ` [PATCH] vt-d: Fix IM bit unmask of Fault Event Control Register in init_vtd_hw() Wei Liu
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