[PATCH] xen/arm: ctxt_switch: Document the erratum #852523 related to Cortex A57

[Julien Grall <julien.grall@citrix.com>]

When restoring the system register state for an AArch32 guest at EL2,
writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57,
which can lead to the guest effectively running into unexpected domain
faults.

Thankfully, we don't hit this erratum in Xen. Nonetheless, document the
code to prevent any introduction of the erratum if the context switch
code is re-ordered.

Link: http://lists.xen.org/archives/html/xen-devel/2015-09/msg01746.html
Signed-off-by: Julien Grall <julien.grall@citrix.com>

---
    The erratum doc is still not updated so this patch is summary of the
    thread [1]. I hope I understood it correctly.

    [1] http://lists.xen.org/archives/html/xen-devel/2015-09/msg01746.html
---
 xen/arch/arm/domain.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 575745c..4349428 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -181,6 +181,12 @@ static void ctxt_switch_to(struct vcpu *n)
     WRITE_SYSREG(n->arch.ttbcr, TCR_EL1);
     WRITE_SYSREG64(n->arch.ttbr0, TTBR0_EL1);
     WRITE_SYSREG64(n->arch.ttbr1, TTBR1_EL1);
+
+    /*
+     * Erratum #852523: DACR32_EL2 must be restored before one of the
+     * following sysregs: SCTLR_EL1, TCR_EL1, TTBR0_EL1, TTBR1_EL1 or
+     * CONTEXTIDR_EL1.
+     */
     if ( is_32bit_domain(n->domain) )
         WRITE_SYSREG(n->arch.dacr, DACR32_EL2);
     WRITE_SYSREG64(n->arch.par, PAR_EL1);
@@ -198,6 +204,10 @@ static void ctxt_switch_to(struct vcpu *n)
     /* Control Registers */
     WRITE_SYSREG(n->arch.cpacr, CPACR_EL1);
 
+    /*
+     * This write to sysreg CONTEXTIDR_EL1 ensure we don't hit the erratum
+     * #852523. I.e DACR32_EL2 is not correctly synchronized.
+     */
     WRITE_SYSREG(n->arch.contextidr, CONTEXTIDR_EL1);
     WRITE_SYSREG(n->arch.tpidr_el0, TPIDR_EL0);
     WRITE_SYSREG(n->arch.tpidrro_el0, TPIDRRO_EL0);
-- 
2.1.4