[PATCH 0/2] xen/x86: Improvements to x86_capability[] handling

[PATCH 0/2] xen/x86: Improvements to x86_capability[] handling

[Andrew Cooper]

More patches as a result of my cpuid levelling improvement work.

These changes are all purely mechanical and neither of these two patches have
any functional change; the compiled binaries are identical other than their
timestamps.

Andrew Cooper (2):
  xen/x86: Helpers for cpu feature manipuation
  xen/x86: Remove assumptions about the layout of x86_capabilities

 xen/arch/x86/boot/head.S         |  2 +-
 xen/arch/x86/boot/trampoline.S   |  2 +-
 xen/arch/x86/cpu/amd.c           |  2 +-
 xen/arch/x86/cpu/centaur.c       |  6 +--
 xen/arch/x86/cpu/common.c        | 22 +++++-----
 xen/arch/x86/efi/efi-boot.h      |  5 ++-
 xen/arch/x86/hvm/hvm.c           | 10 ++---
 xen/arch/x86/mpparse.c           |  6 ++-
 xen/arch/x86/traps.c             |  2 +-
 xen/arch/x86/xstate.c            |  4 +-
 xen/include/asm-x86/amd.h        | 89 +++++++++++++++++++---------------------
 xen/include/asm-x86/asm_defns.h  |  2 +-
 xen/include/asm-x86/cpufeature.h |  8 +++-
 13 files changed, 83 insertions(+), 77 deletions(-)

-- 
2.1.4

[PATCH 1/2] xen/x86: Helpers for cpu feature manipuation

[Andrew Cooper]

Expose them to assembly code, and replace open-coded versions.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
---
 xen/arch/x86/boot/head.S         |  2 +-
 xen/arch/x86/boot/trampoline.S   |  2 +-
 xen/arch/x86/cpu/common.c        |  4 +-
 xen/arch/x86/efi/efi-boot.h      |  2 +-
 xen/arch/x86/hvm/hvm.c           | 10 ++---
 xen/arch/x86/traps.c             |  2 +-
 xen/arch/x86/xstate.c            |  4 +-
 xen/include/asm-x86/amd.h        | 89 +++++++++++++++++++---------------------
 xen/include/asm-x86/asm_defns.h  |  2 +-
 xen/include/asm-x86/cpufeature.h |  7 +++-
 10 files changed, 63 insertions(+), 61 deletions(-)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index f63b349..ac4962b 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -142,7 +142,7 @@ __start:
         mov     %edx,sym_phys(boot_cpu_data)+CPUINFO_FEATURE_OFFSET(X86_FEATURE_LM)
 
         /* Check for availability of long mode. */
-        bt      $X86_FEATURE_LM & 0x1f,%edx
+        bt      $cpufeat_bit(X86_FEATURE_LM),%edx
         jnc     bad_cpu
 
         /* Stash TSC to calculate a good approximation of time-since-boot */
diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S
index 8b0d9c1..c8f32cd 100644
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -89,7 +89,7 @@ trampoline_protmode_entry:
         movl    $MSR_EFER,%ecx
         rdmsr
         or      $EFER_LME|EFER_SCE,%eax   /* Long Mode + SYSCALL/SYSRET */
-        bt      $X86_FEATURE_NX % 32,%edi /* No Execute? */
+        bt      $cpufeat_bit(X86_FEATURE_NX),%edi /* No Execute? */
         jnc     1f
         btsl    $_EFER_NX,%eax  /* No Execute     */
 1:      wrmsr
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index f256444..a5caa84 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -202,7 +202,7 @@ static void __init early_cpu_detect(void)
 	c->x86_mask = tfms & 15;
 	cap0 &= ~cleared_caps[0];
 	cap4 &= ~cleared_caps[4];
-	if (cap0 & (1<<19))
+	if (cap0 & cpufeat_mask(X86_FEATURE_CLFLSH))
 		c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
 	/* Leaf 0x1 capabilities filled in early for Xen. */
 	c->x86_capability[0] = cap0;
@@ -263,7 +263,7 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 	if ( c->cpuid_level >= 0x00000007 ) {
 		u32 dummy;
 		cpuid_count(0x00000007, 0, &dummy, &ebx, &dummy, &dummy);
-		c->x86_capability[X86_FEATURE_FSGSBASE / 32] = ebx;
+		c->x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)] = ebx;
 	}
 }
 
diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index 4c7f383..d8ca862 100644
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -225,7 +225,7 @@ static void __init noreturn efi_arch_post_exit_boot(void)
     asm volatile("pushq $0\n\tpopfq");
     rdmsrl(MSR_EFER, efer);
     efer |= EFER_SCE;
-    if ( cpuid_ext_features & (1 << (X86_FEATURE_NX & 0x1f)) )
+    if ( cpuid_ext_features & cpufeat_mask(X86_FEATURE_NX) )
         efer |= EFER_NX;
     wrmsrl(MSR_EFER, efer);
     write_cr0(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP |
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 3fa2280..965bfbf 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1850,8 +1850,8 @@ static const char * hvm_efer_valid(const struct vcpu *v, uint64_t value,
     }
     else
     {
-        ext1_edx = boot_cpu_data.x86_capability[X86_FEATURE_LM / 32];
-        ext1_ecx = boot_cpu_data.x86_capability[X86_FEATURE_SVM / 32];
+        ext1_edx = boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_LM)];
+        ext1_ecx = boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_SVM)];
     }
 
     /*
@@ -1917,9 +1917,9 @@ static unsigned long hvm_cr4_guest_reserved_bits(const struct vcpu *v,
     }
     else
     {
-        leaf1_edx = boot_cpu_data.x86_capability[X86_FEATURE_VME / 32];
-        leaf1_ecx = boot_cpu_data.x86_capability[X86_FEATURE_PCID / 32];
-        leaf7_0_ebx = boot_cpu_data.x86_capability[X86_FEATURE_FSGSBASE / 32];
+        leaf1_edx = boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_VME)];
+        leaf1_ecx = boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_PCID)];
+        leaf7_0_ebx = boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)];
     }
 
     return ~(unsigned long)
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 8093535..b32f696 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -935,7 +935,7 @@ void pv_cpuid(struct cpu_user_regs *regs)
             goto unsupported;
         if ( regs->_ecx == 1 )
         {
-            a &= boot_cpu_data.x86_capability[X86_FEATURE_XSAVEOPT / 32];
+            a &= boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_XSAVEOPT)];
             if ( !cpu_has_xsaves )
                 b = c = d = 0;
         }
diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c
index 9ddff90..c6238d9 100644
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -326,9 +326,9 @@ void xstate_init(struct cpuinfo_x86 *c)
     eax &= (cpufeat_mask(X86_FEATURE_XSAVEOPT) |
             cpufeat_mask(X86_FEATURE_XSAVEC));
 
-    c->x86_capability[X86_FEATURE_XSAVEOPT / 32] = eax;
+    c->x86_capability[cpufeat_word(X86_FEATURE_XSAVEOPT)] = eax;
 
-    BUG_ON(eax != boot_cpu_data.x86_capability[X86_FEATURE_XSAVEOPT / 32]);
+    BUG_ON(eax != boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_XSAVEOPT)]);
 }
 
 static bool_t valid_xcr0(u64 xcr0)
diff --git a/xen/include/asm-x86/amd.h b/xen/include/asm-x86/amd.h
index 87b6e3e..bb23bea 100644
--- a/xen/include/asm-x86/amd.h
+++ b/xen/include/asm-x86/amd.h
@@ -9,95 +9,92 @@
 
 /* CPUID masked for use by AMD-V Extended Migration */
 
-#define X86_FEATURE_BITPOS(_feature_) ((_feature_) % 32)
-#define __bit(_x_) (1U << X86_FEATURE_BITPOS(_x_))
-
 /* Family 0Fh, Revision C */
 #define AMD_FEATURES_K8_REV_C_ECX  0
-#define AMD_FEATURES_K8_REV_C_EDX (					\
-	__bit(X86_FEATURE_FPU)      | __bit(X86_FEATURE_VME)   |	\
-	__bit(X86_FEATURE_DE)       | __bit(X86_FEATURE_PSE)   |	\
-	__bit(X86_FEATURE_TSC)      | __bit(X86_FEATURE_MSR)   |	\
-	__bit(X86_FEATURE_PAE)      | __bit(X86_FEATURE_MCE)   |	\
-	__bit(X86_FEATURE_CX8)      | __bit(X86_FEATURE_APIC)  |	\
-	__bit(X86_FEATURE_SEP)      | __bit(X86_FEATURE_MTRR)  |	\
-	__bit(X86_FEATURE_PGE)      | __bit(X86_FEATURE_MCA)   | 	\
-	__bit(X86_FEATURE_CMOV)     | __bit(X86_FEATURE_PAT)   |	\
-	__bit(X86_FEATURE_PSE36)    | __bit(X86_FEATURE_CLFLSH)|	\
-	__bit(X86_FEATURE_MMX)      | __bit(X86_FEATURE_FXSR)  | 	\
-	__bit(X86_FEATURE_XMM)      | __bit(X86_FEATURE_XMM2))
-#define AMD_EXTFEATURES_K8_REV_C_ECX  0 
-#define AMD_EXTFEATURES_K8_REV_C_EDX  (					\
-	__bit(X86_FEATURE_FPU)      | __bit(X86_FEATURE_VME)   |	\
-	__bit(X86_FEATURE_DE)       | __bit(X86_FEATURE_PSE)   |	\
-	__bit(X86_FEATURE_TSC)      | __bit(X86_FEATURE_MSR)   |	\
-	__bit(X86_FEATURE_PAE)      | __bit(X86_FEATURE_MCE)   |	\
-	__bit(X86_FEATURE_CX8)      | __bit(X86_FEATURE_APIC)  |	\
-	__bit(X86_FEATURE_SYSCALL)  | __bit(X86_FEATURE_MTRR)  |	\
-	__bit(X86_FEATURE_PGE)      | __bit(X86_FEATURE_MCA)   |	\
-	__bit(X86_FEATURE_CMOV)     | __bit(X86_FEATURE_PAT)   |	\
-	__bit(X86_FEATURE_PSE36)    | __bit(X86_FEATURE_NX)    |	\
-	__bit(X86_FEATURE_MMXEXT)   | __bit(X86_FEATURE_MMX)   |	\
-	__bit(X86_FEATURE_FXSR)     | __bit(X86_FEATURE_LM)    |	\
-	__bit(X86_FEATURE_3DNOWEXT) | __bit(X86_FEATURE_3DNOW))
+#define AMD_FEATURES_K8_REV_C_EDX (					    \
+	cpufeat_mask(X86_FEATURE_FPU)   | cpufeat_mask(X86_FEATURE_VME)   | \
+	cpufeat_mask(X86_FEATURE_DE)    | cpufeat_mask(X86_FEATURE_PSE)   | \
+	cpufeat_mask(X86_FEATURE_TSC)   | cpufeat_mask(X86_FEATURE_MSR)   | \
+	cpufeat_mask(X86_FEATURE_PAE)   | cpufeat_mask(X86_FEATURE_MCE)   | \
+	cpufeat_mask(X86_FEATURE_CX8)   | cpufeat_mask(X86_FEATURE_APIC)  | \
+	cpufeat_mask(X86_FEATURE_SEP)   | cpufeat_mask(X86_FEATURE_MTRR)  | \
+	cpufeat_mask(X86_FEATURE_PGE)   | cpufeat_mask(X86_FEATURE_MCA)   | \
+	cpufeat_mask(X86_FEATURE_CMOV)  | cpufeat_mask(X86_FEATURE_PAT)   | \
+	cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLSH)| \
+	cpufeat_mask(X86_FEATURE_MMX)   | cpufeat_mask(X86_FEATURE_FXSR)  | \
+	cpufeat_mask(X86_FEATURE_XMM)   | cpufeat_mask(X86_FEATURE_XMM2))
+#define AMD_EXTFEATURES_K8_REV_C_ECX  0
+#define AMD_EXTFEATURES_K8_REV_C_EDX  (					       \
+	cpufeat_mask(X86_FEATURE_FPU)	   | cpufeat_mask(X86_FEATURE_VME)   | \
+	cpufeat_mask(X86_FEATURE_DE)	   | cpufeat_mask(X86_FEATURE_PSE)   | \
+	cpufeat_mask(X86_FEATURE_TSC)	   | cpufeat_mask(X86_FEATURE_MSR)   | \
+	cpufeat_mask(X86_FEATURE_PAE)	   | cpufeat_mask(X86_FEATURE_MCE)   | \
+	cpufeat_mask(X86_FEATURE_CX8)	   | cpufeat_mask(X86_FEATURE_APIC)  | \
+	cpufeat_mask(X86_FEATURE_SYSCALL)  | cpufeat_mask(X86_FEATURE_MTRR)  | \
+	cpufeat_mask(X86_FEATURE_PGE)	   | cpufeat_mask(X86_FEATURE_MCA)   | \
+	cpufeat_mask(X86_FEATURE_CMOV)	   | cpufeat_mask(X86_FEATURE_PAT)   | \
+	cpufeat_mask(X86_FEATURE_PSE36)	   | cpufeat_mask(X86_FEATURE_NX)    | \
+	cpufeat_mask(X86_FEATURE_MMXEXT)   | cpufeat_mask(X86_FEATURE_MMX)   | \
+	cpufeat_mask(X86_FEATURE_FXSR)	   | cpufeat_mask(X86_FEATURE_LM)    | \
+	cpufeat_mask(X86_FEATURE_3DNOWEXT) | cpufeat_mask(X86_FEATURE_3DNOW))
 
 /* Family 0Fh, Revision D */
 #define AMD_FEATURES_K8_REV_D_ECX         AMD_FEATURES_K8_REV_C_ECX
 #define AMD_FEATURES_K8_REV_D_EDX         AMD_FEATURES_K8_REV_C_EDX
 #define AMD_EXTFEATURES_K8_REV_D_ECX     (AMD_EXTFEATURES_K8_REV_C_ECX |\
-	__bit(X86_FEATURE_LAHF_LM))
+	cpufeat_mask(X86_FEATURE_LAHF_LM))
 #define AMD_EXTFEATURES_K8_REV_D_EDX     (AMD_EXTFEATURES_K8_REV_C_EDX |\
-	__bit(X86_FEATURE_FFXSR))
+	cpufeat_mask(X86_FEATURE_FFXSR))
 
 /* Family 0Fh, Revision E */
 #define AMD_FEATURES_K8_REV_E_ECX        (AMD_FEATURES_K8_REV_D_ECX |	\
-	__bit(X86_FEATURE_XMM3))
+	cpufeat_mask(X86_FEATURE_XMM3))
 #define AMD_FEATURES_K8_REV_E_EDX        (AMD_FEATURES_K8_REV_D_EDX | 	\
-	__bit(X86_FEATURE_HT))
+	cpufeat_mask(X86_FEATURE_HT))
 #define AMD_EXTFEATURES_K8_REV_E_ECX     (AMD_EXTFEATURES_K8_REV_D_ECX |\
-	__bit(X86_FEATURE_CMP_LEGACY)) 
+	cpufeat_mask(X86_FEATURE_CMP_LEGACY))
 #define AMD_EXTFEATURES_K8_REV_E_EDX      AMD_EXTFEATURES_K8_REV_D_EDX
 
 /* Family 0Fh, Revision F */
 #define AMD_FEATURES_K8_REV_F_ECX        (AMD_FEATURES_K8_REV_E_ECX | 	\
-	__bit(X86_FEATURE_CX16))
+	cpufeat_mask(X86_FEATURE_CX16))
 #define AMD_FEATURES_K8_REV_F_EDX         AMD_FEATURES_K8_REV_E_EDX
 #define AMD_EXTFEATURES_K8_REV_F_ECX     (AMD_EXTFEATURES_K8_REV_E_ECX |\
-	__bit(X86_FEATURE_SVM) | __bit(X86_FEATURE_EXTAPIC) |	        \
-	__bit(X86_FEATURE_CR8_LEGACY))
+	cpufeat_mask(X86_FEATURE_SVM) | cpufeat_mask(X86_FEATURE_EXTAPIC) | \
+	cpufeat_mask(X86_FEATURE_CR8_LEGACY))
 #define AMD_EXTFEATURES_K8_REV_F_EDX     (AMD_EXTFEATURES_K8_REV_E_EDX |\
-	__bit(X86_FEATURE_RDTSCP))
+	cpufeat_mask(X86_FEATURE_RDTSCP))
 
 /* Family 0Fh, Revision G */
 #define AMD_FEATURES_K8_REV_G_ECX         AMD_FEATURES_K8_REV_F_ECX
 #define AMD_FEATURES_K8_REV_G_EDX         AMD_FEATURES_K8_REV_F_EDX
 #define AMD_EXTFEATURES_K8_REV_G_ECX     (AMD_EXTFEATURES_K8_REV_F_ECX |\
-	__bit(X86_FEATURE_3DNOWPREFETCH))
+	cpufeat_mask(X86_FEATURE_3DNOWPREFETCH))
 #define AMD_EXTFEATURES_K8_REV_G_EDX      AMD_EXTFEATURES_K8_REV_F_EDX
 
 /* Family 10h, Revision B */
 #define AMD_FEATURES_FAM10h_REV_B_ECX    (AMD_FEATURES_K8_REV_F_ECX | 	\
-	__bit(X86_FEATURE_POPCNT) | __bit(X86_FEATURE_MWAIT))
+	cpufeat_mask(X86_FEATURE_POPCNT) | cpufeat_mask(X86_FEATURE_MWAIT))
 #define AMD_FEATURES_FAM10h_REV_B_EDX     AMD_FEATURES_K8_REV_F_EDX
 #define AMD_EXTFEATURES_FAM10h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\
-	__bit(X86_FEATURE_ABM) | __bit(X86_FEATURE_SSE4A) | 		\
-	__bit(X86_FEATURE_MISALIGNSSE) | __bit(X86_FEATURE_OSVW) | 	\
-	__bit(X86_FEATURE_IBS))
+	cpufeat_mask(X86_FEATURE_ABM) | cpufeat_mask(X86_FEATURE_SSE4A) | \
+	cpufeat_mask(X86_FEATURE_MISALIGNSSE) | cpufeat_mask(X86_FEATURE_OSVW) |\
+	cpufeat_mask(X86_FEATURE_IBS))
 #define AMD_EXTFEATURES_FAM10h_REV_B_EDX (AMD_EXTFEATURES_K8_REV_F_EDX |\
-	__bit(X86_FEATURE_PAGE1GB))
+	cpufeat_mask(X86_FEATURE_PAGE1GB))
 
 /* Family 10h, Revision C */
 #define AMD_FEATURES_FAM10h_REV_C_ECX     AMD_FEATURES_FAM10h_REV_B_ECX
 #define AMD_FEATURES_FAM10h_REV_C_EDX     AMD_FEATURES_FAM10h_REV_B_EDX
 #define AMD_EXTFEATURES_FAM10h_REV_C_ECX (AMD_EXTFEATURES_FAM10h_REV_B_ECX |\
-	__bit(X86_FEATURE_SKINIT) | __bit(X86_FEATURE_WDT))
+	cpufeat_mask(X86_FEATURE_SKINIT) | cpufeat_mask(X86_FEATURE_WDT))
 #define AMD_EXTFEATURES_FAM10h_REV_C_EDX  AMD_EXTFEATURES_FAM10h_REV_B_EDX
 
 /* Family 11h, Revision B */
 #define AMD_FEATURES_FAM11h_REV_B_ECX     AMD_FEATURES_K8_REV_G_ECX
 #define AMD_FEATURES_FAM11h_REV_B_EDX     AMD_FEATURES_K8_REV_G_EDX
 #define AMD_EXTFEATURES_FAM11h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_G_ECX |\
-	__bit(X86_FEATURE_SKINIT))
+	cpufeat_mask(X86_FEATURE_SKINIT))
 #define AMD_EXTFEATURES_FAM11h_REV_B_EDX  AMD_EXTFEATURES_K8_REV_G_EDX
 
 /* AMD errata checking
diff --git a/xen/include/asm-x86/asm_defns.h b/xen/include/asm-x86/asm_defns.h
index 7c8c2c0..d750f03 100644
--- a/xen/include/asm-x86/asm_defns.h
+++ b/xen/include/asm-x86/asm_defns.h
@@ -137,7 +137,7 @@ void ret_from_intr(void);
 #endif
 
 #define CPUINFO_FEATURE_OFFSET(feature)           \
-        ((((feature) >> 3) & ~3) + CPUINFO_features)
+    (CPUINFO_features + (cpufeat_word(feature) * 4))
 
 #else
 
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index e94b04d..e823954 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -9,6 +9,8 @@
 #define __ASM_I386_CPUFEATURE_H
 #endif
 
+#include <xen/const.h>
+
 #define NCAPINTS	8	/* N 32-bit words worth of info */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
@@ -160,12 +162,15 @@
 #define X86_FEATURE_ADX		(7*32+19) /* ADCX, ADOX instructions */
 #define X86_FEATURE_SMAP	(7*32+20) /* Supervisor Mode Access Prevention */
 
+#define cpufeat_word(idx)	((idx) / 32)
+#define cpufeat_bit(idx)	((idx) % 32)
+#define cpufeat_mask(idx)	(_AC(1, U) << cpufeat_bit(idx))
+
 #if !defined(__ASSEMBLY__) && !defined(X86_FEATURES_ONLY)
 #include <xen/bitops.h>
 
 #define cpu_has(c, bit)		test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)	test_bit(bit, boot_cpu_data.x86_capability)
-#define cpufeat_mask(idx)       (1u << ((idx) & 31))
 
 #define CPUID_MWAIT_LEAF                5
 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
-- 
2.1.4

[PATCH 2/2] xen/x86: Remove assumptions about the layout of x86_capabilities

[Andrew Cooper]

Future work will rearange it, invalidating these assumptions.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
---
 xen/arch/x86/cpu/amd.c           |  2 +-
 xen/arch/x86/cpu/centaur.c       |  6 ++----
 xen/arch/x86/cpu/common.c        | 18 ++++++++++--------
 xen/arch/x86/efi/efi-boot.h      |  3 ++-
 xen/arch/x86/mpparse.c           |  6 ++++--
 xen/include/asm-x86/cpufeature.h |  1 +
 6 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index fd57370..74a0152 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -444,7 +444,7 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
 
 	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
-	__clear_bit(0*32+31, c->x86_capability);
+	__clear_bit(X86_FEATURE_3DNOW_ALT, c->x86_capability);
 	
 	if (c->x86 == 0xf && c->x86_model < 0x14
 	    && cpu_has(c, X86_FEATURE_LAHF_LM)) {
diff --git a/xen/arch/x86/cpu/centaur.c b/xen/arch/x86/cpu/centaur.c
index 66b1995..c0ac117 100644
--- a/xen/arch/x86/cpu/centaur.c
+++ b/xen/arch/x86/cpu/centaur.c
@@ -39,10 +39,8 @@ static void init_c3(struct cpuinfo_x86 *c)
 			printk(KERN_INFO "CPU: Enabled h/w RNG\n");
 		}
 
-		/* store Centaur Extended Feature Flags as
-		 * word 5 of the CPU capability bit array
-		 */
-		c->x86_capability[5] = cpuid_edx(0xC0000001);
+		c->x86_capability[cpufeat_word(X86_FEATURE_XSTORE)]
+                    = cpuid_edx(0xC0000001);
 	}
 
 	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index a5caa84..653b052 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -200,13 +200,13 @@ static void __init early_cpu_detect(void)
 	if (c->x86 >= 0x6)
 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
 	c->x86_mask = tfms & 15;
-	cap0 &= ~cleared_caps[0];
-	cap4 &= ~cleared_caps[4];
+	cap0 &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)];
+	cap4 &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)];
 	if (cap0 & cpufeat_mask(X86_FEATURE_CLFLSH))
 		c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
 	/* Leaf 0x1 capabilities filled in early for Xen. */
-	c->x86_capability[0] = cap0;
-	c->x86_capability[4] = cap4;
+	c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = cap0;
+	c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = cap4;
 }
 
 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
@@ -225,8 +225,8 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 	
 	/* Intel-defined flags: level 0x00000001 */
 	cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
-	c->x86_capability[0] = capability;
-	c->x86_capability[4] = excap;
+	c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = capability;
+	c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = excap;
 	c->x86 = (tfms >> 8) & 15;
 	c->x86_model = (tfms >> 4) & 15;
 	if (c->x86 == 0xf)
@@ -247,8 +247,10 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 	c->extended_cpuid_level = cpuid_eax(0x80000000);
 	if ( (c->extended_cpuid_level & 0xffff0000) == 0x80000000 ) {
 		if ( c->extended_cpuid_level >= 0x80000001 ) {
-			c->x86_capability[1] = cpuid_edx(0x80000001);
-			c->x86_capability[6] = cpuid_ecx(0x80000001);
+			c->x86_capability[cpufeat_word(X86_FEATURE_SYSCALL)]
+				= cpuid_edx(0x80000001);
+			c->x86_capability[cpufeat_word(X86_FEATURE_LAHF_LM)]
+				= cpuid_ecx(0x80000001);
 		}
 		if ( c->extended_cpuid_level >= 0x80000004 )
 			get_model_name(c); /* Default name */
diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index d8ca862..6dbb14d 100644
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -608,7 +608,8 @@ static void __init efi_arch_cpu(void)
     if ( cpuid_eax(0x80000000) > 0x80000000 )
     {
         cpuid_ext_features = cpuid_edx(0x80000001);
-        boot_cpu_data.x86_capability[1] = cpuid_ext_features;
+        boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_SYSCALL)]
+            = cpuid_ext_features;
     }
 }
 
diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
index 8609f4a..dc74e37 100644
--- a/xen/arch/x86/mpparse.c
+++ b/xen/arch/x86/mpparse.c
@@ -495,7 +495,8 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
 	processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
 				   (boot_cpu_data.x86_model << 4) |
 				   boot_cpu_data.x86_mask;
-	processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
+	processor.mpc_featureflag =
+            boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_FPU)];
 	processor.mpc_reserved[0] = 0;
 	processor.mpc_reserved[1] = 0;
 	for (i = 0; i < 2; i++) {
@@ -799,7 +800,8 @@ int __devinit mp_register_lapic (
 	processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
 	processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | 
 		(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
-	processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
+	processor.mpc_featureflag
+            = boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_FPU)];
 	processor.mpc_reserved[0] = 0;
 	processor.mpc_reserved[1] = 0;
 
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index e823954..af127cf 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -45,6 +45,7 @@
 #define X86_FEATURE_ACC		(0*32+29) /* Automatic clock control */
 #define X86_FEATURE_IA64	(0*32+30) /* IA-64 processor */
 #define X86_FEATURE_PBE		(0*32+31) /* Pending Break Enable */
+#define X86_FEATURE_3DNOW_ALT	(0*32+31) /* AMD nonstandard 3DNow (Aliases PBE) */
 
 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
 /* Don't duplicate feature flags which are redundant with Intel! */
-- 
2.1.4

Re: [PATCH 1/2] xen/x86: Helpers for cpu feature manipuation

[Jan Beulich]

>>> On 26.10.15 at 12:17, <andrew.cooper3@citrix.com> wrote:
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -202,7 +202,7 @@ static void __init early_cpu_detect(void)
>  	c->x86_mask = tfms & 15;
>  	cap0 &= ~cleared_caps[0];
>  	cap4 &= ~cleared_caps[4];
> -	if (cap0 & (1<<19))
> +	if (cap0 & cpufeat_mask(X86_FEATURE_CLFLSH))

This one's particularly well spotted! Thanks!

Jan

Re: [PATCH 1/2] xen/x86: Helpers for cpu feature manipuation

[Andrew Cooper]

On 26/10/15 12:06, Jan Beulich wrote:
>>>> On 26.10.15 at 12:17, <andrew.cooper3@citrix.com> wrote:
>> --- a/xen/arch/x86/cpu/common.c
>> +++ b/xen/arch/x86/cpu/common.c
>> @@ -202,7 +202,7 @@ static void __init early_cpu_detect(void)
>>  	c->x86_mask = tfms & 15;
>>  	cap0 &= ~cleared_caps[0];
>>  	cap4 &= ~cleared_caps[4];
>> -	if (cap0 & (1<<19))
>> +	if (cap0 & cpufeat_mask(X86_FEATURE_CLFLSH))
> This one's particularly well spotted! Thanks!

I doubt I have found all instances like this.  I only found this one
because of the associated changes in the subsequent patch.

I will be fixing them as I find them.

~Andrew