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From: Julien Grall <julien.grall@citrix.com>
To: xen-devel@lists.xenproject.org
Cc: Julien Grall <julien.grall@citrix.com>,
	ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com
Subject: [PATCH 0/9] xen/arm: Bunch of fixes for the vGIC emulation
Date: Fri, 13 Nov 2015 11:54:23 +0000	[thread overview]
Message-ID: <1447415672-31633-1-git-send-email-julien.grall@citrix.com> (raw)

Hi all,

The main point of this series is to fix the access to any register when the
user doesn't write at the base offset of the registers.

At the same, I took the opportunity to re-arrange the emulation and dropping
any registers which doesn't exists or not required by the spec.

This series is based on "xen/arm: vgic: Support 32-bit access for 64-bit
register" [1]. I've provided a branch with the 2 series applied:

git://xenbits.xen.org/people/julieng/xen-unstable.git branch gic-emulation-v1

Sincerely yours,

[1] http://lists.xen.org/archives/html/xen-devel/2015-11/msg00782.html

Julien Grall (9):
  xen/arm: vgic-v3: Use the correct offset GICR_IGRPMODR0
  xen/arm: vgic-v3: Only emulate identification registers requested by
    the spec
  xen/arm: vgic: Properly emulate the full register
  xen/arm: vgic-v3: Remove GICR_MOVALLR and GICR_MOVLPIR
  xen/arm: vgic: Re-order the register emulations to match the memory
    map
  xen/arm: vgic-v3: Emulate read to GICD_ICACTIVER<n>
  xen/arm: vgic-v3: Remove spurious return in GICR_INVALLR
  xen/arm: vgic-v3: Don't implement write-only register read as zero
  xen/arm: vgic-v3: Make clear that GICD_*SPI_* registers are reserved

 xen/arch/arm/vgic-v2.c            | 252 +++++++------
 xen/arch/arm/vgic-v3.c            | 720 +++++++++++++++++++++++++-------------
 xen/include/asm-arm/gic_v3_defs.h |  16 +-
 xen/include/asm-arm/vgic-emul.h   |  24 ++
 4 files changed, 654 insertions(+), 358 deletions(-)
 create mode 100644 xen/include/asm-arm/vgic-emul.h

-- 
2.1.4

             reply	other threads:[~2015-11-13 11:56 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-13 11:54 Julien Grall [this message]
2015-11-13 11:54 ` [PATCH 1/9] xen/arm: vgic-v3: Use the correct offset GICR_IGRPMODR0 Julien Grall
2015-11-16 13:20   ` Ian Campbell
2015-11-13 11:54 ` [PATCH 2/9] xen/arm: vgic-v3: Only emulate identification registers requested by the spec Julien Grall
2015-11-16 13:27   ` Ian Campbell
2015-11-18 16:46     ` Julien Grall
2015-11-13 11:54 ` [PATCH 3/9] xen/arm: vgic: Properly emulate the full register Julien Grall
2015-11-16 13:29   ` Ian Campbell
2015-11-13 11:54 ` [PATCH 4/9] xen/arm: vgic-v3: Remove GICR_MOVALLR and GICR_MOVLPIR Julien Grall
2015-11-16 13:33   ` Ian Campbell
2015-11-18 16:58     ` Julien Grall
2015-11-13 11:54 ` [PATCH 5/9] xen/arm: vgic: Re-order the register emulations to match the memory map Julien Grall
2015-11-16 13:35   ` Ian Campbell
2015-11-13 11:54 ` [PATCH 6/9] xen/arm: vgic-v3: Emulate read to GICD_ICACTIVER<n> Julien Grall
2015-11-16 13:36   ` Ian Campbell
2015-11-13 11:54 ` [PATCH 7/9] xen/arm: vgic-v3: Remove spurious return in GICR_INVALLR Julien Grall
2015-11-16 13:36   ` Ian Campbell
2015-11-13 11:54 ` [PATCH 8/9] xen/arm: vgic-v3: Don't implement write-only register read as zero Julien Grall
2015-11-16 13:37   ` Ian Campbell
2015-11-13 11:54 ` [PATCH 9/9] xen/arm: vgic-v3: Make clear that GICD_*SPI_* registers are reserved Julien Grall
2015-11-16 13:39   ` Ian Campbell

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