From: Julien Grall <julien.grall@citrix.com>
To: xen-devel@lists.xenproject.org
Cc: Julien Grall <julien.grall@citrix.com>,
ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com
Subject: [PATCH 1/9] xen/arm: vgic-v3: Use the correct offset GICR_IGRPMODR0
Date: Fri, 13 Nov 2015 11:54:24 +0000 [thread overview]
Message-ID: <1447415672-31633-2-git-send-email-julien.grall@citrix.com> (raw)
In-Reply-To: <1447415672-31633-1-git-send-email-julien.grall@citrix.com>
The offset is 0x0D00 and not 0x0F80.
Also re-order the definition to keep all the definitions ordered.
Signed-off-by: Julien Grall <julien.grall@citrix.com>
---
xen/include/asm-arm/gic_v3_defs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
index 89a3548..34e8b0a 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -96,7 +96,6 @@
/* GICR for SGI's & PPI's */
#define GICR_IGROUPR0 (0x0080)
-#define GICR_IGRPMODR0 (0x0F80)
#define GICR_ISENABLER0 (0x0100)
#define GICR_ICENABLER0 (0x0180)
#define GICR_ISPENDR0 (0x0200)
@@ -107,6 +106,7 @@
#define GICR_IPRIORITYR7 (0x041C)
#define GICR_ICFGR0 (0x0C00)
#define GICR_ICFGR1 (0x0C04)
+#define GICR_IGRPMODR0 (0x0D00)
#define GICR_NSACR (0x0E00)
#define GICR_TYPER_PLPIS (1U << 0)
--
2.1.4
next prev parent reply other threads:[~2015-11-13 11:56 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-13 11:54 [PATCH 0/9] xen/arm: Bunch of fixes for the vGIC emulation Julien Grall
2015-11-13 11:54 ` Julien Grall [this message]
2015-11-16 13:20 ` [PATCH 1/9] xen/arm: vgic-v3: Use the correct offset GICR_IGRPMODR0 Ian Campbell
2015-11-13 11:54 ` [PATCH 2/9] xen/arm: vgic-v3: Only emulate identification registers requested by the spec Julien Grall
2015-11-16 13:27 ` Ian Campbell
2015-11-18 16:46 ` Julien Grall
2015-11-13 11:54 ` [PATCH 3/9] xen/arm: vgic: Properly emulate the full register Julien Grall
2015-11-16 13:29 ` Ian Campbell
2015-11-13 11:54 ` [PATCH 4/9] xen/arm: vgic-v3: Remove GICR_MOVALLR and GICR_MOVLPIR Julien Grall
2015-11-16 13:33 ` Ian Campbell
2015-11-18 16:58 ` Julien Grall
2015-11-13 11:54 ` [PATCH 5/9] xen/arm: vgic: Re-order the register emulations to match the memory map Julien Grall
2015-11-16 13:35 ` Ian Campbell
2015-11-13 11:54 ` [PATCH 6/9] xen/arm: vgic-v3: Emulate read to GICD_ICACTIVER<n> Julien Grall
2015-11-16 13:36 ` Ian Campbell
2015-11-13 11:54 ` [PATCH 7/9] xen/arm: vgic-v3: Remove spurious return in GICR_INVALLR Julien Grall
2015-11-16 13:36 ` Ian Campbell
2015-11-13 11:54 ` [PATCH 8/9] xen/arm: vgic-v3: Don't implement write-only register read as zero Julien Grall
2015-11-16 13:37 ` Ian Campbell
2015-11-13 11:54 ` [PATCH 9/9] xen/arm: vgic-v3: Make clear that GICD_*SPI_* registers are reserved Julien Grall
2015-11-16 13:39 ` Ian Campbell
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