[PATCH 8/9] xen/arm: vgic-v3: Don't implement write-only register read as zero

[Julien Grall <julien.grall@citrix.com>]

A read to a write only register is unknown. Use a memorable value to
differentiate from an actual RAZ register.

Signed-off-by: Julien Grall <julien.grall@citrix.com>
---
 xen/arch/arm/vgic-v3.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index c68afdb..44e926a 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -217,12 +217,12 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
         goto read_impl_defined;
 
     case VREG64(GICR_SETLPIR):
-        /* WO. Read as zero */
-        goto read_as_zero_64;
+        /* WO. Read unknown */
+        goto read_unknown;
 
     case VREG64(GICR_CLRLPIR):
-        /* WO. Read as zero */
-        goto read_as_zero_64;
+        /* WO. Read unknown */
+        goto read_unknown;
 
     case 0x0050:
         goto read_reserved;
@@ -239,15 +239,15 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
         goto read_reserved;
 
     case VREG64(GICR_INVLPIR):
-        /* WO. Read as zero */
-        goto read_as_zero_64;
+        /* WO. Read unknown */
+        goto read_unknown;
 
     case 0x00A8:
         goto read_reserved;
 
     case VREG64(GICR_INVALLR):
-        /* WO. Read as zero */
-        goto read_as_zero_64;
+        /* WO. Read unknown */
+        goto read_unknown;
 
     case 0x00B8:
         goto read_reserved;
@@ -324,6 +324,10 @@ read_reserved:
            v, gicr_reg);
     *r = 0;
     return 1;
+
+read_unknown:
+    *r = vgic_reg64_extract(0xdeadbeafdeadbeaf, info);
+    return 1;
 }
 
 static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info,
-- 
2.1.4