From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH v2 10/11] xen/arm: vgic-v3: Don't implement write-only register read as zero Date: Wed, 18 Nov 2015 17:28:05 +0000 Message-ID: <1447867686-19371-11-git-send-email-julien.grall@citrix.com> References: <1447867686-19371-1-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zz6hT-0000mb-5V for xen-devel@lists.xenproject.org; Wed, 18 Nov 2015 17:39:19 +0000 In-Reply-To: <1447867686-19371-1-git-send-email-julien.grall@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org A read to a write only register is unknown. Use a memorable value to differentiate from an actual RAZ register. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v2: - Add Ian's acked-by --- xen/arch/arm/vgic-v3.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index c68afdb..44e926a 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -217,12 +217,12 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, goto read_impl_defined; case VREG64(GICR_SETLPIR): - /* WO. Read as zero */ - goto read_as_zero_64; + /* WO. Read unknown */ + goto read_unknown; case VREG64(GICR_CLRLPIR): - /* WO. Read as zero */ - goto read_as_zero_64; + /* WO. Read unknown */ + goto read_unknown; case 0x0050: goto read_reserved; @@ -239,15 +239,15 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, goto read_reserved; case VREG64(GICR_INVLPIR): - /* WO. Read as zero */ - goto read_as_zero_64; + /* WO. Read unknown */ + goto read_unknown; case 0x00A8: goto read_reserved; case VREG64(GICR_INVALLR): - /* WO. Read as zero */ - goto read_as_zero_64; + /* WO. Read unknown */ + goto read_unknown; case 0x00B8: goto read_reserved; @@ -324,6 +324,10 @@ read_reserved: v, gicr_reg); *r = 0; return 1; + +read_unknown: + *r = vgic_reg64_extract(0xdeadbeafdeadbeaf, info); + return 1; } static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, -- 2.1.4