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From: Julien Grall <julien.grall@citrix.com>
To: xen-devel@lists.xenproject.org
Cc: Julien Grall <julien.grall@citrix.com>,
	ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com
Subject: [PATCH v2 11/11] xen/arm: vgic-v3: Make clear that GICD_*SPI_* registers are reserved
Date: Wed, 18 Nov 2015 17:28:06 +0000	[thread overview]
Message-ID: <1447867686-19371-12-git-send-email-julien.grall@citrix.com> (raw)
In-Reply-To: <1447867686-19371-1-git-send-email-julien.grall@citrix.com>

Our vGIC emulation have GICD_TYPER.MBIS set to 0 which means that
GICD_*SPI_* registers are reserved. Implement them using the *_reserved
labels.

Also, implement theses registers for the read part.

Signed-off-by: Julien Grall <julien.grall@citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---

    Changes in v2:
        - Add Ian's acked-by
        - Fix typoes
---
 xen/arch/arm/vgic-v3.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 44e926a..985e866 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -951,15 +951,31 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
     case VRANGE32(0x0020, 0x003C):
         goto read_impl_defined;
 
+    case VREG32(GICD_SETSPI_NSR):
+        /* Message based SPI is not implemented */
+        goto read_reserved;
+
     case VREG32(0x0044):
         goto read_reserved;
 
+    case VREG32(GICD_CLRSPI_NSR):
+        /* Message based SPI is not implemented */
+        goto read_reserved;
+
     case VREG32(0x004C):
         goto read_reserved;
 
+    case VREG32(GICD_SETSPI_SR):
+        /* Message based SPI is not implemented */
+        goto read_reserved;
+
     case VREG32(0x0054):
         goto read_reserved;
 
+    case VREG32(GICD_CLRSPI_SR):
+        /* Message based SPI is not implemented */
+        goto read_reserved;
+
     case VRANGE32(0x005C, 0x007C):
         goto read_reserved;
 
@@ -1125,28 +1141,28 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info,
 
     case VREG32(GICD_SETSPI_NSR):
         /* Message based SPI is not implemented */
-        goto write_ignore_32;
+        goto write_reserved;
 
     case VREG32(0x0044):
         goto write_reserved;
 
     case VREG32(GICD_CLRSPI_NSR):
         /* Message based SPI is not implemented */
-        goto write_ignore_32;
+        goto write_reserved;
 
     case VREG32(0x004C):
         goto write_reserved;
 
     case VREG32(GICD_SETSPI_SR):
         /* Message based SPI is not implemented */
-        goto write_ignore_32;
+        goto write_reserved;
 
     case VREG32(0x0054):
         goto write_reserved;
 
     case VREG32(GICD_CLRSPI_SR):
         /* Message based SPI is not implemented */
-        goto write_ignore_32;
+        goto write_reserved;
 
     case VRANGE32(0x005C, 0x007C):
         goto write_reserved;
-- 
2.1.4

      parent reply	other threads:[~2015-11-18 17:39 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-18 17:27 [PATCH v2 00/11] xen/arm: Bunch of fixes for the vGIC emulation Julien Grall
2015-11-18 17:27 ` [PATCH v2 01/11] xen/arm: vgic-v2: Implement correctly ICFGR{0, 1} read-only Julien Grall
2015-11-24 17:14   ` Ian Campbell
2015-11-25 12:29     ` Ian Campbell
2015-11-30 12:11       ` Julien Grall
2015-11-18 17:27 ` [PATCH v2 02/11] xen/arm: vgic-v3: Don't try to emulate IROUTER which doesn't exist in the spec Julien Grall
2015-11-24 17:17   ` Ian Campbell
2015-11-30 12:13     ` Julien Grall
2015-11-18 17:27 ` [PATCH v2 03/11] xen/arm: vgic-v3: Use the correct offset GICR_IGRPMODR0 Julien Grall
2015-11-18 17:27 ` [PATCH v2 04/11] xen/arm: vgic-v3: Only emulate identification registers required by the spec Julien Grall
2015-11-18 17:28 ` [PATCH v2 05/11] xen/arm: vgic: Properly emulate the full register Julien Grall
2015-11-25  9:26   ` Shannon Zhao
2015-11-25 12:15     ` unhandled word causes Xen crash with recent Linux kernels, was: " Stefano Stabellini
2015-11-25 12:26       ` Ian Campbell
2015-11-30 12:22         ` Julien Grall
2015-11-30 12:38           ` Ian Campbell
2015-12-03 10:50             ` Stefano Stabellini
2015-11-30 12:18       ` Julien Grall
2015-11-18 17:28 ` [PATCH v2 06/11] xen/arm: vgic-v3: Remove GICR_MOVALLR and GICR_MOVLPIR Julien Grall
2015-11-18 17:28 ` [PATCH v2 07/11] xen/arm: vgic: Re-order the register emulations to match the memory map Julien Grall
2015-11-18 17:28 ` [PATCH v2 08/11] xen/arm: vgic-v3: Emulate read to GICD_ICACTIVER<n> Julien Grall
2015-11-18 17:28 ` [PATCH v2 09/11] xen/arm: vgic-v3: Remove spurious return in GICR_INVALLR Julien Grall
2015-11-18 17:28 ` [PATCH v2 10/11] xen/arm: vgic-v3: Don't implement write-only register read as zero Julien Grall
2015-11-18 17:28 ` Julien Grall [this message]

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