From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH v2 11/11] xen/arm: vgic-v3: Make clear that GICD_*SPI_* registers are reserved Date: Wed, 18 Nov 2015 17:28:06 +0000 Message-ID: <1447867686-19371-12-git-send-email-julien.grall@citrix.com> References: <1447867686-19371-1-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zz6hS-0000mV-GZ for xen-devel@lists.xenproject.org; Wed, 18 Nov 2015 17:39:18 +0000 In-Reply-To: <1447867686-19371-1-git-send-email-julien.grall@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Our vGIC emulation have GICD_TYPER.MBIS set to 0 which means that GICD_*SPI_* registers are reserved. Implement them using the *_reserved labels. Also, implement theses registers for the read part. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v2: - Add Ian's acked-by - Fix typoes --- xen/arch/arm/vgic-v3.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 44e926a..985e866 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -951,15 +951,31 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, case VRANGE32(0x0020, 0x003C): goto read_impl_defined; + case VREG32(GICD_SETSPI_NSR): + /* Message based SPI is not implemented */ + goto read_reserved; + case VREG32(0x0044): goto read_reserved; + case VREG32(GICD_CLRSPI_NSR): + /* Message based SPI is not implemented */ + goto read_reserved; + case VREG32(0x004C): goto read_reserved; + case VREG32(GICD_SETSPI_SR): + /* Message based SPI is not implemented */ + goto read_reserved; + case VREG32(0x0054): goto read_reserved; + case VREG32(GICD_CLRSPI_SR): + /* Message based SPI is not implemented */ + goto read_reserved; + case VRANGE32(0x005C, 0x007C): goto read_reserved; @@ -1125,28 +1141,28 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info, case VREG32(GICD_SETSPI_NSR): /* Message based SPI is not implemented */ - goto write_ignore_32; + goto write_reserved; case VREG32(0x0044): goto write_reserved; case VREG32(GICD_CLRSPI_NSR): /* Message based SPI is not implemented */ - goto write_ignore_32; + goto write_reserved; case VREG32(0x004C): goto write_reserved; case VREG32(GICD_SETSPI_SR): /* Message based SPI is not implemented */ - goto write_ignore_32; + goto write_reserved; case VREG32(0x0054): goto write_reserved; case VREG32(GICD_CLRSPI_SR): /* Message based SPI is not implemented */ - goto write_ignore_32; + goto write_reserved; case VRANGE32(0x005C, 0x007C): goto write_reserved; -- 2.1.4