From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH v2 06/11] xen/arm: vgic-v3: Remove GICR_MOVALLR and GICR_MOVLPIR Date: Wed, 18 Nov 2015 17:28:01 +0000 Message-ID: <1447867686-19371-7-git-send-email-julien.grall@citrix.com> References: <1447867686-19371-1-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zz6Y5-0007IY-GU for xen-devel@lists.xenproject.org; Wed, 18 Nov 2015 17:29:37 +0000 In-Reply-To: <1447867686-19371-1-git-send-email-julien.grall@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org The 2 registers are not described in the software spec (ARM IHI 0069A) and their offsets are marked "implementation defined". Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Note that I didn't combine the 2 cases because a follow-up patch will add reserved registers between the 2 cases. Changes in v2: - Add Ian's acked-by --- xen/arch/arm/vgic-v3.c | 20 ++++++++------------ xen/include/asm-arm/gic_v3_defs.h | 2 -- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 892104d..28f075a 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -241,13 +241,11 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, *r = vgic_reg32_extract(GICR_SYNCR_NOT_BUSY, info); return 1; - case VREG64(GICR_MOVLPIR): - /* WO Read as zero */ - goto read_as_zero_64; + case VREG64(0x0100): + goto read_impl_defined; - case VREG64(GICR_MOVALLR): - /* WO Read as zero */ - goto read_as_zero_64; + case VREG64(0x0110): + goto read_impl_defined; case 0xFFD0 ... 0xFFE4: /* Implementation defined identification registers */ @@ -348,13 +346,11 @@ static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, /* RO */ goto write_ignore_32; - case VREG64(GICR_MOVLPIR): - /* LPI is not implemented */ - goto write_ignore_64; + case VREG64(0x0100): + goto write_impl_defined; - case VREG64(GICR_MOVALLR): - /* LPI is not implemented */ - goto write_ignore_64; + case VREG64(0x0110): + goto write_impl_defined; case 0xFFD0 ... 0xFFE4: /* Implementation defined identification registers */ diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 5a6938c..6d98491 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -77,8 +77,6 @@ #define GICR_INVLPIR (0x00A0) #define GICR_INVALLR (0x00B0) #define GICR_SYNCR (0x00C0) -#define GICR_MOVLPIR (0x100) -#define GICR_MOVALLR (0x0110) #define GICR_PIDR2 GICD_PIDR2 /* GICR for SGI's & PPI's */ -- 2.1.4