From: Ian Campbell <ian.campbell@citrix.com>
To: Julien Grall <julien.grall@citrix.com>, xen-devel@lists.xenproject.org
Cc: stefano.stabellini@eu.citrix.com
Subject: Re: [PATCH v6 3/6] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0
Date: Wed, 25 Nov 2015 11:34:26 +0000 [thread overview]
Message-ID: <1448451266.17688.71.camel@citrix.com> (raw)
In-Reply-To: <1447864963-21577-4-git-send-email-julien.grall@citrix.com>
On Wed, 2015-11-18 at 16:42 +0000, Julien Grall wrote:
> The current implementation ignores the whole write if one of the field is
> 0. Although, based on the spec (4.3.12 IHI 0048B.b), 0 is a valid value
> when:
> - The interrupt is not wired in the distributor. From the Xen
> point of view, it means that the corresponding bit is not set in
> d->arch.vgic.allocated_irqs.
> - The user wants to disable the IRQ forwarding in the distributor.
> I.e the IRQ stays pending in the distributor and never received by
> the guest.
>
> Implementing the later will require more work in Xen because we always
> assume the interrupt is forwarded to a valid vCPU. So for now, ignore
> any field where the value is 0.
>
> The emulation of the write access of ITARGETSR has been reworked and
> moved to a new function because it would have been difficult to
> implement properly the behavior with the current code.
>
> The new implementation is breaking the register in 4 distinct bytes. For
> each byte, it will check the validity of the target list, find the new
> target, migrate the interrupt and store the value if necessary.
>
> In the new implementation there is nearly no distinction of the access
> size to avoid having too many different path which is harder to test.
>
> Signed-off-by: Julien Grall <julien.grall@citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
> ---
> This change used to be embedded in "xen/arm: vgic: Optimize the way
> to store the target vCPU in the rank". It has been moved out to
> avoid having too much functional changes in a single patch.
>
> I'm not sure if this patch should be backported to Xen 4.6. Without
> it any guest writing 0 in one the field won't be able to migrate
> other interrupts. Although, in all the use case I've seen, the guest
> is read ITARGETSR first and write-back the value with the
> corresponding byte changed.
Lets park it until someone reports they are tripping over this then.
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next prev parent reply other threads:[~2015-11-25 11:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-18 16:42 [PATCH v6 0/6] xen/arm: vgic: Support 32-bit access for 64-bit registers Julien Grall
2015-11-18 16:42 ` [PATCH v6 1/6] xen/arm: vgic-v2: Implement correctly ITARGETSR0 - ITARGETSR7 read-only Julien Grall
2015-11-18 16:42 ` [PATCH v6 2/6] xen/arm: vgic-v2: Handle correctly byte write in ITARGETSR Julien Grall
2015-11-18 16:42 ` [PATCH v6 3/6] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0 Julien Grall
2015-11-25 11:34 ` Ian Campbell [this message]
2015-11-18 16:42 ` [PATCH v6 4/6] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Julien Grall
2015-11-25 11:37 ` Ian Campbell
2015-11-30 13:32 ` Julien Grall
2015-11-30 13:55 ` Ian Campbell
2015-11-30 14:02 ` Julien Grall
2015-11-18 16:42 ` [PATCH v6 5/6] xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register Julien Grall
2015-11-18 16:42 ` [PATCH v6 6/6] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers Julien Grall
2015-11-25 12:29 ` [PATCH v6 0/6] xen/arm: vgic: " Ian Campbell
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