From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: jun.nakajima@intel.com, kevin.tian@intel.com, keir@xen.org,
jbeulich@suse.com, andrew.cooper3@citrix.com
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>,
dietmar.hahn@ts.fujitsu.com, xen-devel@lists.xen.org
Subject: [PATCH v2 0/2] Be more strict about writing to Intel VPMU registers
Date: Wed, 23 Dec 2015 11:52:24 -0500 [thread overview]
Message-ID: <1450889546-12837-1-git-send-email-boris.ostrovsky@oracle.com> (raw)
* Add more checks when writing VPMU control registers
* Explicitly disable PEBS since calculating reserved bits in MSR_IA32_PEBS_ENABLE
is somewhat non-trivial (and pointless since PEBS is not supported)
Boris Ostrovsky (2):
x86/VPMU: Check more carefully which bits are allowed to be written
to MSRs
x86/VPMU: Don't allow any non-zero writes to MSR_IA32_PEBS_ENABLE
xen/arch/x86/cpu/vpmu_intel.c | 31 ++++++++++++++++++++++---------
1 files changed, 22 insertions(+), 9 deletions(-)
next reply other threads:[~2015-12-23 16:52 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-23 16:52 Boris Ostrovsky [this message]
2015-12-23 16:52 ` [PATCH v2 1/2] x86/VPMU: Check more carefully which bits are allowed to be written to MSRs Boris Ostrovsky
2015-12-23 16:52 ` [PATCH v2 2/2] x86/VPMU: Don't allow any non-zero writes to MSR_IA32_PEBS_ENABLE Boris Ostrovsky
2015-12-25 1:42 ` Tian, Kevin
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