From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: [PATCH v2 0/2] Be more strict about writing to Intel VPMU registers Date: Wed, 23 Dec 2015 11:52:24 -0500 Message-ID: <1450889546-12837-1-git-send-email-boris.ostrovsky@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: jun.nakajima@intel.com, kevin.tian@intel.com, keir@xen.org, jbeulich@suse.com, andrew.cooper3@citrix.com Cc: Boris Ostrovsky , dietmar.hahn@ts.fujitsu.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org * Add more checks when writing VPMU control registers * Explicitly disable PEBS since calculating reserved bits in MSR_IA32_PEBS_ENABLE is somewhat non-trivial (and pointless since PEBS is not supported) Boris Ostrovsky (2): x86/VPMU: Check more carefully which bits are allowed to be written to MSRs x86/VPMU: Don't allow any non-zero writes to MSR_IA32_PEBS_ENABLE xen/arch/x86/cpu/vpmu_intel.c | 31 ++++++++++++++++++++++--------- 1 files changed, 22 insertions(+), 9 deletions(-)