[PATCHv2] x86: don't flush the whole cache when changing cachability

[David Vrabel <david.vrabel@citrix.com>]

Introduce the FLUSH_CACHE_BY_VA flag to flush_area_mask() and friends
to say that it is safe to use CLFLUSH (i.e., the virtual address is
still valid).

Use this when changing the cachability of the Xen direct mappings (in
response to the guest changing the cachability of its mappings). This
significantly improves performance by avoiding an expensive WBINVD.

This fixes a performance regression introduced by
c61a6f74f80eb36ed83a82f713db3143159b9009 (x86: enforce consistent
cachability of MMIO mappings), the fix for XSA-154.

e.g., A set_memory_wc() call in Linux:

before: 4097 us
after:    47 us

Signed-off-by: David Vrabel <david.vrabel@citrix.com>
---
v2:
- Only set FLUSH_VA_VALID if virt is in [DIRECTMAP_VIRT_START,
  DIRECTMAP_VIRT_END).
---
 xen/arch/x86/flushtlb.c        | 3 ++-
 xen/arch/x86/mm.c              | 5 +++++
 xen/include/asm-x86/flushtlb.h | 2 ++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c
index 582a1e2..ee61aab 100644
--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -140,7 +140,8 @@ unsigned int flush_area_local(const void *va, unsigned int flags)
         if ( order < (BITS_PER_LONG - PAGE_SHIFT) )
             sz = 1UL << (order + PAGE_SHIFT);
 
-        if ( !(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) &&
+        if ( (!(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) ||
+              (flags & FLUSH_VA_VALID)) &&
              c->x86_clflush_size && c->x86_cache_size && sz &&
              ((sz >> 10) < c->x86_cache_size) )
         {
diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c
index 36c4487..60e99a0 100644
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -5641,7 +5641,12 @@ int map_pages_to_xen(
         flush_flags |= FLUSH_TLB_GLOBAL;       \
     if ( (flags & _PAGE_PRESENT) &&            \
          (((o_) ^ flags) & PAGE_CACHE_ATTRS) ) \
+    {                                          \
         flush_flags |= FLUSH_CACHE;            \
+        if ( virt >= DIRECTMAP_VIRT_START &&   \
+             virt < DIRECTMAP_VIRT_END )       \
+            flush_flags |= FLUSH_VA_VALID;     \
+    }                                          \
 } while (0)
 
     while ( nr_mfns != 0 )
diff --git a/xen/include/asm-x86/flushtlb.h b/xen/include/asm-x86/flushtlb.h
index 4ea31c2..2e7ed6b 100644
--- a/xen/include/asm-x86/flushtlb.h
+++ b/xen/include/asm-x86/flushtlb.h
@@ -85,6 +85,8 @@ void write_cr3(unsigned long cr3);
 #define FLUSH_TLB_GLOBAL 0x200
  /* Flush data caches */
 #define FLUSH_CACHE      0x400
+ /* VA for the flush has a valid mapping */
+#define FLUSH_VA_VALID   0x800
 
 /* Flush local TLBs/caches. */
 unsigned int flush_area_local(const void *va, unsigned int flags);
-- 
2.1.4


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