[PATCH 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64

[PATCH 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64

[Wei Chen]

Current MPIDR_HWID_MASK is using the bit definition of ARM32 MPIDR.
This value is not correct while Xen is running on ARM64.
Now, we add a correct value for this marco on ARM64. But this value
is not a valid 64-bit immediate which can be encoded in mov instruction.
So we have to use ldr to load this value to register.

Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
---
 xen/arch/arm/arm64/head.S       | 2 +-
 xen/include/asm-arm/processor.h | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index d5831f2..3090beb 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -270,7 +270,7 @@ common_start:
         tbz   x0, _MPIDR_SMP, 1f     /* Multiprocessor extension not supported? */
         tbnz  x0, _MPIDR_UP, 1f      /* Uniprocessor system? */
 
-        mov   x13, #(~MPIDR_HWID_MASK)
+        ldr   x13, =(~MPIDR_HWID_MASK)
         bic   x24, x0, x13           /* Mask out flags to get CPU ID */
 1:
 
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index b4cce7e..284ad6a 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -18,7 +18,11 @@
 #define MPIDR_SMP           (_AC(1,U) << _MPIDR_SMP)
 #define MPIDR_AFF0_SHIFT    (0)
 #define MPIDR_AFF0_MASK     (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
+#ifdef CONFIG_ARM_64
+#define MPIDR_HWID_MASK     _AC(0xff00ffffff,UL)
+#else
 #define MPIDR_HWID_MASK     _AC(0xffffff,U)
+#endif
 #define MPIDR_INVALID       (~MPIDR_HWID_MASK)
 #define MPIDR_LEVEL_BITS    (8)
 
-- 
2.7.4


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Re: [PATCH 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64

[Julien Grall]

Hi Wei,

Title: "Fix the MPIDR_HWID_MASK value for ARM64".

On 25/05/16 03:09, Wei Chen wrote:
> Current MPIDR_HWID_MASK is using the bit definition of ARM32 MPIDR.

s/Current/Currently/

> This value is not correct while Xen is running on ARM64.

I think s/while/when/

> Now, we add a correct value for this marco on ARM64. But this value

s/marco/macro/

> is not a valid 64-bit immediate which can be encoded in mov instruction.
> So we have to use ldr to load this value to register.

You need to explain what is the valid value, i.e there is 4 level of 
affinity whilst AArch32 has only 3. It would be good to mention the spec 
too.

>
> Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
> ---
>   xen/arch/arm/arm64/head.S       | 2 +-
>   xen/include/asm-arm/processor.h | 4 ++++
>   2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index d5831f2..3090beb 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -270,7 +270,7 @@ common_start:
>           tbz   x0, _MPIDR_SMP, 1f     /* Multiprocessor extension not supported? */
>           tbnz  x0, _MPIDR_UP, 1f      /* Uniprocessor system? */
>
> -        mov   x13, #(~MPIDR_HWID_MASK)
> +        ldr   x13, =(~MPIDR_HWID_MASK)
>           bic   x24, x0, x13           /* Mask out flags to get CPU ID */
>   1:
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index b4cce7e..284ad6a 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -18,7 +18,11 @@
>   #define MPIDR_SMP           (_AC(1,U) << _MPIDR_SMP)
>   #define MPIDR_AFF0_SHIFT    (0)
>   #define MPIDR_AFF0_MASK     (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
> +#ifdef CONFIG_ARM_64
> +#define MPIDR_HWID_MASK     _AC(0xff00ffffff,UL)
> +#else
>   #define MPIDR_HWID_MASK     _AC(0xffffff,U)
> +#endif
>   #define MPIDR_INVALID       (~MPIDR_HWID_MASK)
>   #define MPIDR_LEVEL_BITS    (8)
>
>

Regards,

-- 
Julien Grall

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