From: "Xu, Quan" <quan.xu@intel.com>
To: xen-devel@lists.xen.org
Cc: Kevin Tian <kevin.tian@intel.com>,
dario.faggioli@citrix.com, Feng Wu <feng.wu@intel.com>,
Jan Beulich <jbeulich@suse.com>, Quan Xu <quan.xu@intel.com>
Subject: [PATCH v12 3/6] vt-d: convert conditionals of qi_ctrl->qinval_maddr into ASSERT()s
Date: Fri, 24 Jun 2016 13:51:55 +0800 [thread overview]
Message-ID: <1466747518-54402-4-git-send-email-quan.xu@intel.com> (raw)
In-Reply-To: <1466747518-54402-1-git-send-email-quan.xu@intel.com>
From: Quan Xu <quan.xu@intel.com>
QI ought to have got disabled if any of the IOMMU table setup
failed. A QI function (other than enable_qinval) is unreachable
when qi_ctrl->qinval_maddr is zero.
Signed-off-by: Quan Xu <quan.xu@intel.com>
CC: Jan Beulich <jbeulich@suse.com>
CC: Kevin Tian <kevin.tian@intel.com>
CC: Feng Wu <feng.wu@intel.com>
---
xen/drivers/passthrough/vtd/qinval.c | 52 ++++++++++++++++--------------------
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/xen/drivers/passthrough/vtd/qinval.c b/xen/drivers/passthrough/vtd/qinval.c
index 46c4c8f..4492b29 100644
--- a/xen/drivers/passthrough/vtd/qinval.c
+++ b/xen/drivers/passthrough/vtd/qinval.c
@@ -204,10 +204,9 @@ static int __must_check invalidate_sync(struct iommu *iommu,
{
struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu);
- if ( qi_ctrl->qinval_maddr )
- return queue_invalidate_wait(iommu, 0, 1, 1, flush_dev_iotlb);
+ ASSERT(qi_ctrl->qinval_maddr);
- return 0;
+ return queue_invalidate_wait(iommu, 0, 1, 1, flush_dev_iotlb);
}
int qinval_device_iotlb_sync(struct iommu *iommu,
@@ -297,10 +296,11 @@ static int __must_check flush_context_qi(void *_iommu, u16 did,
u16 sid, u8 fm, u64 type,
bool_t flush_non_present_entry)
{
- int ret = 0;
struct iommu *iommu = (struct iommu *)_iommu;
struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu);
+ ASSERT(qi_ctrl->qinval_maddr);
+
/*
* In the non-present entry flush case, if hardware doesn't cache
* non-present entry we do nothing and if hardware cache non-present
@@ -315,11 +315,8 @@ static int __must_check flush_context_qi(void *_iommu, u16 did,
did = 0;
}
- if ( qi_ctrl->qinval_maddr != 0 )
- ret = queue_invalidate_context_sync(iommu, did, sid, fm,
- type >> DMA_CCMD_INVL_GRANU_OFFSET);
-
- return ret;
+ return queue_invalidate_context_sync(iommu, did, sid, fm,
+ type >> DMA_CCMD_INVL_GRANU_OFFSET);
}
static int __must_check flush_iotlb_qi(void *_iommu, u16 did, u64 addr,
@@ -328,10 +325,12 @@ static int __must_check flush_iotlb_qi(void *_iommu, u16 did, u64 addr,
bool_t flush_dev_iotlb)
{
u8 dr = 0, dw = 0;
- int ret = 0;
+ int ret = 0, rc;
struct iommu *iommu = (struct iommu *)_iommu;
struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu);
+ ASSERT(qi_ctrl->qinval_maddr);
+
/*
* In the non-present entry flush case, if hardware doesn't cache
* non-present entry we do nothing and if hardware cache non-present
@@ -346,28 +345,23 @@ static int __must_check flush_iotlb_qi(void *_iommu, u16 did, u64 addr,
did = 0;
}
- if ( qi_ctrl->qinval_maddr != 0 )
+ /* use queued invalidation */
+ if (cap_write_drain(iommu->cap))
+ dw = 1;
+ if (cap_read_drain(iommu->cap))
+ dr = 1;
+ /* Need to conside the ih bit later */
+ rc = queue_invalidate_iotlb_sync(iommu,
+ type >> DMA_TLB_FLUSH_GRANU_OFFSET,
+ dr, dw, did, size_order, 0, addr);
+ if ( !ret )
+ ret = rc;
+
+ if ( flush_dev_iotlb )
{
- int rc;
-
- /* use queued invalidation */
- if (cap_write_drain(iommu->cap))
- dw = 1;
- if (cap_read_drain(iommu->cap))
- dr = 1;
- /* Need to conside the ih bit later */
- rc = queue_invalidate_iotlb_sync(iommu,
- type >> DMA_TLB_FLUSH_GRANU_OFFSET,
- dr, dw, did, size_order, 0, addr);
+ rc = dev_invalidate_iotlb(iommu, did, addr, size_order, type);
if ( !ret )
ret = rc;
-
- if ( flush_dev_iotlb )
- {
- rc = dev_invalidate_iotlb(iommu, did, addr, size_order, type);
- if ( !ret )
- ret = rc;
- }
}
return ret;
}
--
1.9.1
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next prev parent reply other threads:[~2016-06-24 5:51 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-24 5:51 [PATCH v12 0/6] VT-d Device-TLB flush issue Xu, Quan
2016-06-24 5:51 ` [PATCH v12 1/6] IOMMU: add a timeout parameter for device IOTLB invalidation Xu, Quan
2016-06-24 11:30 ` Tian, Kevin
2016-06-27 8:03 ` Jan Beulich
2016-06-27 8:19 ` Xu, Quan
2016-06-27 8:28 ` Jan Beulich
2016-06-27 8:34 ` Xu, Quan
2016-06-24 5:51 ` [PATCH v12 2/6] vt-d: synchronize for Device-TLB flush one by one Xu, Quan
2016-06-24 11:33 ` Tian, Kevin
2016-06-24 5:51 ` Xu, Quan [this message]
2016-06-24 11:35 ` [PATCH v12 3/6] vt-d: convert conditionals of qi_ctrl->qinval_maddr into ASSERT()s Tian, Kevin
2016-06-24 5:51 ` [PATCH v12 4/6] IOMMU/x86: using a struct pci_dev* instead of SBDF Xu, Quan
2016-06-24 11:46 ` Tian, Kevin
2016-06-26 8:57 ` Xu, Quan
2016-06-26 10:32 ` Xu, Quan
2016-06-29 1:59 ` Tian, Kevin
2016-06-27 8:17 ` Jan Beulich
2016-06-27 8:25 ` Jan Beulich
2016-06-27 11:11 ` Xu, Quan
2016-06-27 15:19 ` Jan Beulich
2016-06-28 1:31 ` Xu, Quan
2016-06-24 5:51 ` [PATCH v12 5/6] IOMMU: move the domain crash logic up to the generic IOMMU layer Xu, Quan
2016-06-24 11:48 ` Tian, Kevin
2016-06-26 8:58 ` Xu, Quan
2016-06-27 8:18 ` Jan Beulich
2016-06-24 5:51 ` [PATCH v12 6/6] vt-d: fix vt-d Device-TLB flush timeout issue Xu, Quan
2016-06-24 11:55 ` Tian, Kevin
2016-06-24 12:54 ` Jan Beulich
2016-06-26 9:18 ` Xu, Quan
2016-06-27 7:56 ` Jan Beulich
2016-06-27 8:24 ` Jan Beulich
2016-06-27 12:56 ` Xu, Quan
2016-06-27 15:21 ` Jan Beulich
2016-06-28 7:06 ` Xu, Quan
2016-06-28 7:24 ` Jan Beulich
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