From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: wei.liu2@citrix.com, he.chen@linux.intel.com,
andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com,
Yi Sun <yi.y.sun@linux.intel.com>,
jbeulich@suse.com, chao.p.peng@linux.intel.com
Subject: [PATCH v3 04/15] x86: refactor psr: Encapsulate 'cbm_len' and 'cbm_max'
Date: Tue, 25 Oct 2016 11:40:52 +0800 [thread overview]
Message-ID: <1477366863-5246-5-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com>
'cbm_len' and 'cbm_max' are CAT/CDP specific feature HW info.
So encapsulate them into 'struct psr_cat_hw_info'. If new
feature is supported, we can define other structure to save
its HW info.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/psr.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index a0342ce..97f1c33 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -26,9 +26,14 @@
/* Per spec, the maximum COS register number is 128. */
#define MAX_COS_REG_NUM 128
-struct psr_cat_socket_info {
+/* CAT/CDP HW info data structure. */
+struct psr_cat_hw_info {
unsigned int cbm_len;
unsigned int cos_max;
+};
+
+struct psr_cat_socket_info {
+ struct psr_cat_hw_info l3_info;
/*
* Store the values of COS registers:
* CAT uses 1 entry for one COS ID;
@@ -235,7 +240,7 @@ static inline void psr_assoc_init(void)
if ( test_bit(socket, cat_socket_enable) )
psra->cos_mask = ((1ull << get_count_order(
- cat_socket_info[socket].cos_max)) - 1) << 32;
+ cat_socket_info[socket].l3_info.cos_max)) - 1) << 32;
}
if ( psr_cmt_enabled() || psra->cos_mask )
@@ -299,8 +304,8 @@ int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
if ( IS_ERR(info) )
return PTR_ERR(info);
- *cbm_len = info->cbm_len;
- *cos_max = info->cos_max;
+ *cbm_len = info->l3_info.cbm_len;
+ *cos_max = info->l3_info.cos_max;
*flags = 0;
if ( cdp_is_enabled(socket) )
@@ -465,14 +470,14 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
if ( IS_ERR(info) )
return PTR_ERR(info);
- if ( !psr_check_cbm(info->cbm_len, cbm) )
+ if ( !psr_check_cbm(info->l3_info.cbm_len, cbm) )
return -EINVAL;
if ( !cdp_enabled && (type == PSR_CBM_TYPE_L3_CODE ||
type == PSR_CBM_TYPE_L3_DATA) )
return -ENXIO;
- cos_max = info->cos_max;
+ cos_max = info->l3_info.cos_max;
old_cos = d->arch.psr_cos_ids[socket];
ref = info->cos_ref;
@@ -617,11 +622,11 @@ static void cat_cpu_init(void)
{
cpuid_count(PSR_CPUID_LEVEL_CAT, 1, &eax, &ebx, &ecx, &edx);
info = cat_socket_info + socket;
- info->cbm_len = (eax & 0x1f) + 1;
- info->cos_max = min(opt_cos_max, edx & 0xffff);
+ info->l3_info.cbm_len = (eax & 0x1f) + 1;
+ info->l3_info.cos_max = min(opt_cos_max, edx & 0xffff);
/* cos=0 is reserved as default cbm(all ones). */
- info->cos_reg_val[0] = (1ull << info->cbm_len) - 1;
+ info->cos_reg_val[0] = (1ull << info->l3_info.cbm_len) - 1;
spin_lock_init(&info->ref_lock);
@@ -631,23 +636,23 @@ static void cat_cpu_init(void)
cdp_socket_enable && !test_bit(socket, cdp_socket_enable) )
{
/* CODE */
- get_cdp_code(info, 0) = (1ull << info->cbm_len) - 1;
+ get_cdp_code(info, 0) = (1ull << info->l3_info.cbm_len) - 1;
/* DATA */
- get_cdp_data(info, 0) = (1ull << info->cbm_len) - 1;
+ get_cdp_data(info, 0) = (1ull << info->l3_info.cbm_len) - 1;
/* We only write mask1 since mask0 is always all ones by default. */
- wrmsrl(MSR_IA32_PSR_L3_MASK(1), (1ull << info->cbm_len) - 1);
+ wrmsrl(MSR_IA32_PSR_L3_MASK(1), (1ull << info->l3_info.cbm_len) - 1);
rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT));
/* Cut half of cos_max when CDP is enabled. */
- info->cos_max >>= 1;
+ info->l3_info.cos_max >>= 1;
set_bit(socket, cdp_socket_enable);
}
printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u, CDP:%s\n",
- socket, info->cos_max, info->cbm_len,
+ socket, info->l3_info.cos_max, info->l3_info.cbm_len,
cdp_is_enabled(socket) ? "on" : "off");
}
}
--
2.7.4
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next prev parent reply other threads:[~2016-10-25 2:33 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-25 3:40 [PATCH v3 00/15] Enable L2 Cache Allocation Technology Yi Sun
2016-10-25 3:40 ` [PATCH v3 01/15] docs: L2 Cache Allocation Technology (CAT) feature document Yi Sun
2016-10-25 13:37 ` Jan Beulich
2016-10-26 1:01 ` Yi Sun
2016-10-30 15:51 ` Meng Xu
2016-11-01 4:40 ` Yi Sun
2016-11-11 21:33 ` Konrad Rzeszutek Wilk
2016-11-14 2:15 ` Yi Sun
2016-11-25 17:19 ` Dario Faggioli
2016-11-29 5:20 ` Yi Sun
2016-11-29 12:25 ` Dario Faggioli
2016-11-25 17:39 ` Dario Faggioli
2016-11-29 4:52 ` Yi Sun
2016-11-29 12:22 ` Dario Faggioli
2016-11-30 1:42 ` Yi Sun
2016-10-25 3:40 ` [PATCH v3 02/15] x86: refactor psr: Split 'ref' out Yi Sun
2016-11-25 15:19 ` Jan Beulich
2016-10-25 3:40 ` [PATCH v3 03/15] x86: refactor psr: Remove 'struct psr_cat_cbm' Yi Sun
2016-11-25 15:45 ` Jan Beulich
2016-10-25 3:40 ` Yi Sun [this message]
2016-11-25 16:27 ` [PATCH v3 04/15] x86: refactor psr: Encapsulate 'cbm_len' and 'cbm_max' Jan Beulich
2016-11-25 16:57 ` Jan Beulich
2016-11-29 4:38 ` Yi Sun
2016-11-29 9:43 ` Jan Beulich
2016-11-30 9:08 ` Yi Sun
2016-11-30 9:42 ` Jan Beulich
2016-11-30 10:22 ` Yi Sun
2016-10-25 3:40 ` [PATCH v3 05/15] x86: refactor psr: Use 'feat_mask' to record featues enabled Yi Sun
2016-11-25 16:36 ` Jan Beulich
2016-10-25 3:40 ` [PATCH v3 06/15] x86: refactor psr: Create feature list Yi Sun
2016-10-25 3:40 ` [PATCH v3 07/15] x86: refactor psr: Implement feature operations structure Yi Sun
2016-10-25 3:40 ` [PATCH v3 08/15] x86: refactor psr: Implement get hw info callback function Yi Sun
2016-10-25 3:40 ` [PATCH v3 09/15] x86: refactor psr: Implement get value " Yi Sun
2016-10-25 3:40 ` [PATCH v3 10/15] x86: refactor psr: Implement function to get the max cos_max Yi Sun
2016-10-25 3:40 ` [PATCH v3 11/15] x86: refactor psr: Implement set value callback function Yi Sun
2016-10-25 3:41 ` [PATCH v3 12/15] x86: Implement L2 CAT in psr.c Yi Sun
2016-10-25 3:41 ` [PATCH v3 13/15] x86: Add L2 CAT interfaces in domctl Yi Sun
2016-10-25 3:41 ` [PATCH v3 14/15] x86: Add L2 CAT interfaces in sysctl Yi Sun
2016-10-25 3:41 ` [PATCH v3 15/15] tools & docs: add L2 CAT support in tools and docs Yi Sun
2016-11-09 1:28 ` [PATCH v3 00/15] Enable L2 Cache Allocation Technology Yi Sun
2016-11-09 8:37 ` Jan Beulich
2016-11-10 1:56 ` Yi Sun
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