From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Xen-devel <xen-devel@lists.xen.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Paul Durrant <paul.durrant@citrix.com>,
Jan Beulich <JBeulich@suse.com>
Subject: [PATCH 7/8] x86/emul: Support CPUID fauilting via a speculative MSR read
Date: Mon, 5 Dec 2016 10:09:30 +0000 [thread overview]
Message-ID: <1480932571-23547-8-git-send-email-andrew.cooper3@citrix.com> (raw)
In-Reply-To: <1480932571-23547-1-git-send-email-andrew.cooper3@citrix.com>
Use the new speculative read support to query MSR_INTEL_MISC_FEATURES for
active CPUID faulting, without raising #GP as a side effect.
This removes the need for every cpuid() emulation hook to individually support
CPUID faulting.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Paul Durrant <paul.durrant@citrix.com>
Jan: Probably worth waiting to rebase over your changes moving the
architectrual defines elsewhere
---
xen/arch/x86/hvm/emulate.c | 9 ---------
xen/arch/x86/x86_emulate/x86_emulate.c | 16 +++++++++++++---
xen/arch/x86/x86_emulate/x86_emulate.h | 7 +------
3 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index bce0b00..1a132e7 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -1567,15 +1567,6 @@ int hvmemul_cpuid(
unsigned int *edx,
struct x86_emulate_ctxt *ctxt)
{
- /*
- * x86_emulate uses this function to query CPU features for its own internal
- * use. Make sure we're actually emulating CPUID before emulating CPUID
- * faulting.
- */
- if ( ctxt->opcode == X86EMUL_OPC(0x0f, 0xa2) &&
- hvm_check_cpuid_faulting(current) )
- return X86EMUL_EXCEPTION;
-
hvm_funcs.cpuid_intercept(eax, ebx, ecx, edx);
return X86EMUL_OKAY;
}
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 5cba7ec..67495eb 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -406,6 +406,8 @@ typedef union {
/* MSRs. */
#define MSR_TSC 0x00000010
+#define MSR_INTEL_MISC_FEATURES 0x00000140
+#define MISC_FEATURES_CPUID_FAULTING (1 << 0)
#define MSR_SYSENTER_CS 0x00000174
#define MSR_SYSENTER_ESP 0x00000175
#define MSR_SYSENTER_EIP 0x00000176
@@ -5044,13 +5046,21 @@ x86_emulate(
src.val = x86_seg_fs;
goto pop_seg;
- case X86EMUL_OPC(0x0f, 0xa2): /* cpuid */ {
+ case X86EMUL_OPC(0x0f, 0xa2): /* cpuid */
+ {
unsigned int eax = _regs.eax, ebx = _regs.ebx;
unsigned int ecx = _regs.ecx, edx = _regs.edx;
+ uint64_t misc_features;
+
fail_if(ops->cpuid == NULL);
+ generate_exception_if(
+ ops->read_msr &&
+ ops->read_msr(MSR_INTEL_MISC_FEATURES,
+ &misc_features, true, ctxt) == X86EMUL_OKAY &&
+ (misc_features & MISC_FEATURES_CPUID_FAULTING) &&
+ !mode_ring0(), EXC_GP, 0); /* CPUID Faulting? */
+
rc = ops->cpuid(&eax, &ebx, &ecx, &edx, ctxt);
- generate_exception_if(rc == X86EMUL_EXCEPTION,
- EXC_GP, 0); /* CPUID Faulting? */
if ( rc != X86EMUL_OKAY )
goto done;
_regs.eax = eax; _regs.ebx = ebx;
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emulate/x86_emulate.h
index 89cf20d..46c863f 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.h
+++ b/xen/arch/x86/x86_emulate/x86_emulate.h
@@ -395,12 +395,7 @@ struct x86_emulate_ops
int (*wbinvd)(
struct x86_emulate_ctxt *ctxt);
- /*
- * cpuid: Emulate CPUID via given set of EAX-EDX inputs/outputs.
- *
- * May return X86EMUL_EXCEPTION, which causes the emulator to inject
- * #GP[0]. Used to implement CPUID faulting.
- */
+ /* cpuid: Emulate CPUID via given set of EAX-EDX inputs/outputs. */
int (*cpuid)(
unsigned int *eax,
unsigned int *ebx,
--
2.1.4
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next prev parent reply other threads:[~2016-12-05 10:09 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-05 10:09 [PATCH 0/8] Misc further emulation work Andrew Cooper
2016-12-05 10:09 ` [PATCH 1/8] x86/shadow: Drop stale adjustment in the PAE second-half search Andrew Cooper
2016-12-05 10:16 ` Tim Deegan
2016-12-05 13:07 ` Andrew Cooper
2016-12-05 10:09 ` [PATCH 2/8] x86/emul: Debugging improvements to the test harness Andrew Cooper
2016-12-05 12:00 ` Jan Beulich
2016-12-05 13:08 ` Andrew Cooper
2016-12-05 10:09 ` [PATCH 3/8] x86/hvm: Assert some expectations in hvm_inject_event() Andrew Cooper
2016-12-05 12:01 ` Jan Beulich
2016-12-05 10:09 ` [PATCH 4/8] x86/emul: Drop the last remaining uses of bool_t Andrew Cooper
2016-12-05 12:02 ` Jan Beulich
2016-12-05 10:09 ` [PATCH 5/8] x86/hvm: Don't raise #GP behind the emulators back for MSR accesses Andrew Cooper
2016-12-05 12:10 ` Jan Beulich
2016-12-05 16:29 ` Andrew Cooper
2016-12-05 17:08 ` Jan Beulich
2016-12-06 6:16 ` Tian, Kevin
2016-12-05 10:09 ` [PATCH 6/8] x86/emul: Support speculative MSR reads Andrew Cooper
2016-12-05 13:03 ` Paul Durrant
2016-12-05 13:25 ` Jan Beulich
2016-12-05 10:09 ` Andrew Cooper [this message]
2016-12-05 13:06 ` [PATCH 7/8] x86/emul: Support CPUID fauilting via a speculative MSR read Paul Durrant
2016-12-05 13:35 ` Jan Beulich
2016-12-05 10:09 ` [PATCH 8/8] x86/emul: Implement the STAC and CLAC instructions Andrew Cooper
2016-12-05 13:45 ` Jan Beulich
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