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From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: wei.liu2@citrix.com, konrad.wilk@oracle.com,
	andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
	he.chen@linux.intel.com, ian.jackson@eu.citrix.com,
	Yi Sun <yi.y.sun@linux.intel.com>,
	mengxu@cis.upenn.edu, jbeulich@suse.com,
	chao.p.peng@linux.intel.com
Subject: [PATCH RESEND v5 20/24] x86: L2 CAT: implement set value flow.
Date: Thu, 19 Jan 2017 14:01:22 +0800	[thread overview]
Message-ID: <1484805686-7249-21-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1484805686-7249-1-git-send-email-yi.y.sun@linux.intel.com>

This patch implements L2 CAT set value related callback functions
and domctl interface.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v5:
    - remove type check in callback function.
    - modify return value of callback functions because we do not need them
      to return number of entries the feature uses. In caller, we call
      'get_cos_num' to get the number of entries the feature uses.
    - remove 'l2_cat_get_cos_max_from_type'.
    - rename 'l2_cat_exceeds_cos_max' to 'l2_cat_fits_cos_max'.
---
 xen/arch/x86/domctl.c           |  6 +++
 xen/arch/x86/psr.c              | 92 +++++++++++++++++++++++++++++++++++++++++
 xen/include/asm-x86/msr-index.h |  1 +
 xen/include/public/domctl.h     |  1 +
 4 files changed, 100 insertions(+)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index af6153d..2767c6a 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1382,6 +1382,12 @@ long arch_do_domctl(
                               PSR_CBM_TYPE_L3_DATA);
             break;
 
+        case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
+            ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+                              domctl->u.psr_cat_op.data,
+                              PSR_CBM_TYPE_L2);
+            break;
+
         case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
             ret = psr_get_val(d, domctl->u.psr_cat_op.target,
                               &domctl->u.psr_cat_op.data,
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 1fad540..13d85e0 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -741,10 +741,102 @@ static bool l2_cat_get_val(const struct feat_node *feat, unsigned int cos,
     return true;
 }
 
+static unsigned int l2_cat_get_cos_num(const struct feat_node *feat)
+{
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+static int l2_cat_get_old_val(uint64_t val[],
+                              const struct feat_node *feat,
+                              unsigned int old_cos)
+{
+    if ( old_cos > feat->info.l2_cat_info.cos_max )
+        /* Use default value. */
+        old_cos = 0;
+
+    val[0] = feat->cos_reg_val[old_cos];
+
+    return 0;
+}
+
+static int l2_cat_set_new_val(uint64_t val[],
+                              const struct feat_node *feat,
+                              enum cbm_type type,
+                              uint64_t m)
+{
+    if ( !psr_check_cbm(feat->info.l2_cat_info.cbm_len, m) )
+        return -EINVAL;
+
+    val[0] = m;
+
+    return 0;
+}
+
+static int l2_cat_compare_val(const uint64_t val[],
+                              const struct feat_node *feat,
+                              unsigned int cos, bool *found)
+{
+    uint64_t l2_def_cbm;
+
+    l2_def_cbm = (1ull << feat->info.l2_cat_info.cbm_len) - 1;
+
+    if ( cos > feat->info.l2_cat_info.cos_max )
+    {
+        if ( val[0] != l2_def_cbm )
+        {
+            *found = false;
+            return -ENOENT;
+        }
+        *found = true;
+    }
+    else
+        *found = (val[0] == feat->cos_reg_val[cos]);
+
+    return 0;
+}
+
+static bool l2_cat_fits_cos_max(const uint64_t val[],
+                                const struct feat_node *feat,
+                                unsigned int cos)
+{
+    uint64_t l2_def_cbm;
+
+    l2_def_cbm = (1ull << feat->info.l2_cat_info.cbm_len) - 1;
+
+    if ( cos > feat->info.l2_cat_info.cos_max &&
+         val[0] != l2_def_cbm )
+            /*
+             * Exceed cos_max and value to set is not default,
+             * return error.
+             */
+            return false;
+
+    return true;
+}
+
+static int l2_cat_write_msr(unsigned int cos, const uint64_t val[],
+                            struct feat_node *feat)
+{
+    if ( cos > feat->info.l2_cat_info.cos_max )
+        return -EINVAL;
+
+    feat->cos_reg_val[cos] = val[0];
+    wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val[0]);
+
+    return 0;
+}
+
 struct feat_ops l2_cat_ops = {
     .get_cos_max = l2_cat_get_cos_max,
     .get_feat_info = l2_cat_get_feat_info,
     .get_val = l2_cat_get_val,
+    .get_cos_num = l2_cat_get_cos_num,
+    .get_old_val = l2_cat_get_old_val,
+    .set_new_val = l2_cat_set_new_val,
+    .compare_val = l2_cat_compare_val,
+    .fits_cos_max = l2_cat_fits_cos_max,
+    .write_msr = l2_cat_write_msr,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 98dbff1..a41e63a 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -343,6 +343,7 @@
 #define MSR_IA32_PSR_L3_MASK(n)	(0x00000c90 + (n))
 #define MSR_IA32_PSR_L3_MASK_CODE(n)	(0x00000c90 + (n) * 2 + 1)
 #define MSR_IA32_PSR_L3_MASK_DATA(n)	(0x00000c90 + (n) * 2)
+#define MSR_IA32_PSR_L2_MASK(n)		(0x00000d10 + (n))
 
 /* Intel Model 6 */
 #define MSR_P6_PERFCTR(n)		(0x000000c1 + (n))
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 8c183ba..523a2cd 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1138,6 +1138,7 @@ struct xen_domctl_psr_cat_op {
 #define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA    3
 #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE    4
 #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA    5
+#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM     6
 #define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM     7
     uint32_t cmd;       /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
     uint32_t target;    /* IN */
-- 
1.9.1


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  parent reply	other threads:[~2017-01-19  6:03 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-19  6:01 [PATCH RESEND v5 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document Yi Sun
2017-01-20  9:39   ` Tian, Kevin
2017-01-22  2:15     ` Yi Sun
2017-02-08  6:45       ` Tian, Kevin
2017-01-30 18:10   ` Konrad Rzeszutek Wilk
2017-01-30 20:39     ` Konrad Rzeszutek Wilk
2017-02-04  7:24       ` Yi Sun
2017-02-04  7:06     ` Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 02/24] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-01-30 22:05   ` Konrad Rzeszutek Wilk
2017-01-19  6:01 ` [PATCH RESEND v5 03/24] x86: refactor psr: implement main data structures Yi Sun
2017-01-30 22:20   ` Konrad Rzeszutek Wilk
2017-01-31 10:10     ` Jan Beulich
2017-01-31 14:12       ` Konrad Rzeszutek Wilk
2017-01-31 15:07         ` Jan Beulich
2017-01-31 17:32           ` Konrad Rzeszutek Wilk
2017-02-05  1:53     ` Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 04/24] x86: refactor psr: implement CPU init and free flow Yi Sun
2017-01-31  2:44   ` Konrad Rzeszutek Wilk
2017-01-31 10:14     ` Jan Beulich
2017-01-31 14:13       ` Konrad Rzeszutek Wilk
2017-01-31 10:53     ` Andrew Cooper
2017-01-19  6:01 ` [PATCH RESEND v5 05/24] x86: refactor psr: implement Domain init/free and schedule flows Yi Sun
2017-01-31 19:52   ` Konrad Rzeszutek Wilk
2017-01-19  6:01 ` [PATCH RESEND v5 06/24] x86: refactor psr: implement get hw info flow Yi Sun
2017-01-31 20:17   ` Konrad Rzeszutek Wilk
2017-01-19  6:01 ` [PATCH RESEND v5 07/24] x86: refactor psr: implement get value flow Yi Sun
2017-01-31 20:29   ` Konrad Rzeszutek Wilk
2017-02-07  2:47     ` Yi Sun
2017-02-07 13:56       ` Konrad Rzeszutek Wilk
2017-01-19  6:01 ` [PATCH RESEND v5 08/24] x86: refactor psr: set value: implement framework Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 09/24] x86: refactor psr: set value: assemble features value array Yi Sun
2017-01-31 20:57   ` Konrad Rzeszutek Wilk
2017-02-07  2:51     ` Yi Sun
2017-02-07 13:57       ` Konrad Rzeszutek Wilk
2017-01-19  6:01 ` [PATCH RESEND v5 10/24] x86: refactor psr: set value: implement cos finding flow Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 11/24] x86: refactor psr: set value: implement cos id picking flow Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 12/24] x86: refactor psr: set value: implement write msr flow Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 13/24] x86: refactor psr: implement CPU init and free flow for CDP Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 14/24] x86: refactor psr: implement get hw info " Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 15/24] x86: refactor psr: implement get value " Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 16/24] x86: refactor psr: implement set value callback functions " Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 17/24] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 18/24] x86: L2 CAT: implement get hw info flow Yi Sun
2017-01-19  6:01 ` [PATCH RESEND v5 19/24] x86: L2 CAT: implement get value flow Yi Sun
2017-01-19  6:01 ` Yi Sun [this message]
2017-01-19  6:01 ` [PATCH RESEND v5 21/24] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-01-27 15:18   ` Wei Liu
2017-01-19  6:01 ` [PATCH RESEND v5 22/24] tools: L2 CAT: support show cbm " Yi Sun
2017-01-27 15:18   ` Wei Liu
2017-01-19  6:01 ` [PATCH RESEND v5 23/24] tools: L2 CAT: support set " Yi Sun
2017-01-27 15:18   ` Wei Liu
2017-01-19  6:01 ` [PATCH RESEND v5 24/24] docs: add L2 CAT description in docs Yi Sun
2017-01-27 15:18   ` Wei Liu

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