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* [PATCH v2] x86/time: Adjust init-time handling of pit0_ticks
@ 2017-02-07 18:51 Andrew Cooper
  2017-02-08 13:10 ` Jan Beulich
  0 siblings, 1 reply; 3+ messages in thread
From: Andrew Cooper @ 2017-02-07 18:51 UTC (permalink / raw)
  To: Xen-devel; +Cc: Andrew Cooper, Jan Beulich

There is no need for the volatile cast in the timer interrupt; the compiler
may not elide the update.  This reduces the generated assembly from a read,
local modify, write to a single add instruction.

Drop the memory barriers from timer_irq_works(), as they are not needed.
pit0_ticks is only modified by timer_interrupt() running on the same CPU, so
that is required is a volatile reference to prevent the compiler from eliding
the second read.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>

v2:
 * Update commit message
---
 xen/arch/x86/io_apic.c | 6 ++----
 xen/arch/x86/time.c    | 2 +-
 xen/include/xen/lib.h  | 2 ++
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 33e5927..f989978 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -1485,8 +1485,7 @@ static int __init timer_irq_works(void)
 {
     unsigned long t1, flags;
 
-    t1 = pit0_ticks;
-    mb();
+    t1 = ACCESS_ONCE(pit0_ticks);
 
     local_save_flags(flags);
     local_irq_enable();
@@ -1501,8 +1500,7 @@ static int __init timer_irq_works(void)
      * might have cached one ExtINT interrupt.  Finally, at
      * least one tick may be lost due to delays.
      */
-    mb();
-    if (pit0_ticks - t1 > 4)
+    if ( (ACCESS_ONCE(pit0_ticks) - t1) > 4 )
         return 1;
 
     return 0;
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index d3b0c69..699dfb6 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -197,7 +197,7 @@ static void timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
         return;
 
     /* Only for start-of-day interruopt tests in io_apic.c. */
-    (*(volatile unsigned long *)&pit0_ticks)++;
+    pit0_ticks++;
 
     /* Rough hack to allow accurate timers to sort-of-work with no APIC. */
     if ( !cpu_has_apic )
diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
index d1171b7..1976e4b 100644
--- a/xen/include/xen/lib.h
+++ b/xen/include/xen/lib.h
@@ -56,6 +56,8 @@
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]) + __must_be_array(x))
 
+#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
+
 #define MASK_EXTR(v, m) (((v) & (m)) / ((m) & -(m)))
 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m))
 
-- 
2.1.4


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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] x86/time: Adjust init-time handling of pit0_ticks
  2017-02-07 18:51 [PATCH v2] x86/time: Adjust init-time handling of pit0_ticks Andrew Cooper
@ 2017-02-08 13:10 ` Jan Beulich
  2017-02-08 13:12   ` Andrew Cooper
  0 siblings, 1 reply; 3+ messages in thread
From: Jan Beulich @ 2017-02-08 13:10 UTC (permalink / raw)
  To: Andrew Cooper; +Cc: Xen-devel

>>> On 07.02.17 at 19:51, <andrew.cooper3@citrix.com> wrote:
> There is no need for the volatile cast in the timer interrupt; the compiler
> may not elide the update.  This reduces the generated assembly from a read,
> local modify, write to a single add instruction.
> 
> Drop the memory barriers from timer_irq_works(), as they are not needed.
> pit0_ticks is only modified by timer_interrupt() running on the same CPU, so
> that is required is a volatile reference to prevent the compiler from eliding
> the second read.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Reviewed-by: Jan Beulich <jbeulich@suse.com>

Is there an "all" missing at the beginning of the last line of the
description?

Jan


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^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] x86/time: Adjust init-time handling of pit0_ticks
  2017-02-08 13:10 ` Jan Beulich
@ 2017-02-08 13:12   ` Andrew Cooper
  0 siblings, 0 replies; 3+ messages in thread
From: Andrew Cooper @ 2017-02-08 13:12 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Xen-devel

On 08/02/17 13:10, Jan Beulich wrote:
>>>> On 07.02.17 at 19:51, <andrew.cooper3@citrix.com> wrote:
>> There is no need for the volatile cast in the timer interrupt; the compiler
>> may not elide the update.  This reduces the generated assembly from a read,
>> local modify, write to a single add instruction.
>>
>> Drop the memory barriers from timer_irq_works(), as they are not needed.
>> pit0_ticks is only modified by timer_interrupt() running on the same CPU, so
>> that is required is a volatile reference to prevent the compiler from eliding
>> the second read.
>>
>> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Reviewed-by: Jan Beulich <jbeulich@suse.com>
>
> Is there an "all" missing at the beginning of the last line of the
> description?

Yes.  Fixed.

Thanks.

~Andrew

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2017-02-07 18:51 [PATCH v2] x86/time: Adjust init-time handling of pit0_ticks Andrew Cooper
2017-02-08 13:10 ` Jan Beulich
2017-02-08 13:12   ` Andrew Cooper

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