From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Xen-devel <xen-devel@lists.xen.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Jan Beulich <JBeulich@suse.com>
Subject: [PATCH v2 1/9] x86/cpuid: Sort cpu_has_* predicates by feature number
Date: Thu, 16 Mar 2017 16:31:35 +0000 [thread overview]
Message-ID: <1489681903-28119-2-git-send-email-andrew.cooper3@citrix.com> (raw)
In-Reply-To: <1489681903-28119-1-git-send-email-andrew.cooper3@citrix.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
v2:
* New
---
xen/include/asm-x86/cpufeature.h | 117 ++++++++++++++++++++++-----------------
1 file changed, 66 insertions(+), 51 deletions(-)
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index b3d613f..5978783 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -29,65 +29,80 @@
#define CPUID_PM_LEAF 6
#define CPUID6_ECX_APERFMPERF_CAPABILITY 0x1
-#define cpu_has_fpu 1
-#define cpu_has_de 1
-#define cpu_has_pse 1
-#define cpu_has_pge 1
-#define cpu_has_pat 1
-#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
-#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
-#define cpu_has_mtrr 1
-#define cpu_has_mmx 1
-#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3)
-#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3)
-#define cpu_has_sse4_1 boot_cpu_has(X86_FEATURE_SSE4_1)
-#define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2)
-#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
-#define cpu_has_popcnt boot_cpu_has(X86_FEATURE_POPCNT)
-#define cpu_has_aesni boot_cpu_has(X86_FEATURE_AESNI)
-#define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT)
-#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
-#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
-#define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB)
-#define cpu_has_fsgsbase boot_cpu_has(X86_FEATURE_FSGSBASE)
-#define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF)
-#define cpu_has_smep boot_cpu_has(X86_FEATURE_SMEP)
-#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
-#define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL))
-#define cpu_has_ffxsr ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
- && boot_cpu_has(X86_FEATURE_FFXSR))
-#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
+/* CPUID level 0x00000001.edx */
+#define cpu_has_fpu 1
+#define cpu_has_de 1
+#define cpu_has_pse 1
+#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
+#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
+#define cpu_has_mtrr 1
+#define cpu_has_pge 1
+#define cpu_has_pat 1
+#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
+#define cpu_has_mmx 1
+#define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT)
+
+/* CPUID level 0x00000001.ecx */
+#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3)
+#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
+#define cpu_has_monitor boot_cpu_has(X86_FEATURE_MONITOR)
+#define cpu_has_vmx boot_cpu_has(X86_FEATURE_VMX)
+#define cpu_has_eist boot_cpu_has(X86_FEATURE_EIST)
+#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3)
+#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
+#define cpu_has_pdcm boot_cpu_has(X86_FEATURE_PDCM)
#define cpu_has_pcid boot_cpu_has(X86_FEATURE_PCID)
+#define cpu_has_sse4_1 boot_cpu_has(X86_FEATURE_SSE4_1)
+#define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2)
+#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
+#define cpu_has_popcnt boot_cpu_has(X86_FEATURE_POPCNT)
+#define cpu_has_aesni boot_cpu_has(X86_FEATURE_AESNI)
#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
+#define cpu_has_rdrand boot_cpu_has(X86_FEATURE_RDRAND)
+#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
+
+/* CPUID level 0x80000001.edx */
+#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
+#define cpu_has_ffxsr ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
+ && boot_cpu_has(X86_FEATURE_FFXSR))
+#define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB)
+#define cpu_has_rdtscp boot_cpu_has(X86_FEATURE_RDTSCP)
+
+/* CPUID level 0x80000001.ecx */
+#define cpu_has_cmp_legacy boot_cpu_has(X86_FEATURE_CMP_LEGACY)
+#define cpu_has_svm boot_cpu_has(X86_FEATURE_SVM)
+#define cpu_has_sse4a boot_cpu_has(X86_FEATURE_SSE4A)
#define cpu_has_lwp boot_cpu_has(X86_FEATURE_LWP)
+#define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM)
+
+/* CPUID level 0x0000000D:1.eax */
+#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT)
+#define cpu_has_xsavec boot_cpu_has(X86_FEATURE_XSAVEC)
+#define cpu_has_xgetbv1 boot_cpu_has(X86_FEATURE_XGETBV1)
+#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
+
+/* CPUID level 0x00000007:0.ebx */
+#define cpu_has_fsgsbase boot_cpu_has(X86_FEATURE_FSGSBASE)
#define cpu_has_bmi1 boot_cpu_has(X86_FEATURE_BMI1)
+#define cpu_has_hle boot_cpu_has(X86_FEATURE_HLE)
+#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
+#define cpu_has_smep boot_cpu_has(X86_FEATURE_SMEP)
#define cpu_has_bmi2 boot_cpu_has(X86_FEATURE_BMI2)
+#define cpu_has_rtm boot_cpu_has(X86_FEATURE_RTM)
+#define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL))
#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
+#define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED)
+#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
+#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
+
+/* CPUID level 0x80000007.edx */
+#define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC)
+
+/* Synthesized. */
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
-#define cpu_has_rdtscp boot_cpu_has(X86_FEATURE_RDTSCP)
-#define cpu_has_svm boot_cpu_has(X86_FEATURE_SVM)
-#define cpu_has_vmx boot_cpu_has(X86_FEATURE_VMX)
-#define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING)
-#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
-#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT)
-#define cpu_has_xsavec boot_cpu_has(X86_FEATURE_XSAVEC)
-#define cpu_has_xgetbv1 boot_cpu_has(X86_FEATURE_XGETBV1)
-#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
-#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
-#define cpu_has_monitor boot_cpu_has(X86_FEATURE_MONITOR)
-#define cpu_has_eist boot_cpu_has(X86_FEATURE_EIST)
-#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
-#define cpu_has_rdrand boot_cpu_has(X86_FEATURE_RDRAND)
-#define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED)
-#define cpu_has_cmp_legacy boot_cpu_has(X86_FEATURE_CMP_LEGACY)
-#define cpu_has_sse4a boot_cpu_has(X86_FEATURE_SSE4A)
-#define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM)
-#define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC)
-#define cpu_has_hle boot_cpu_has(X86_FEATURE_HLE)
-#define cpu_has_rtm boot_cpu_has(X86_FEATURE_RTM)
-#define cpu_has_pdcm boot_cpu_has(X86_FEATURE_PDCM)
-#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
+#define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING)
+#define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF)
enum _cache_type {
CACHE_TYPE_NULL = 0,
--
2.1.4
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next prev parent reply other threads:[~2017-03-16 16:31 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-16 16:31 [PATCH v2 0/9] Fixes to pagetable handling Andrew Cooper
2017-03-16 16:31 ` Andrew Cooper [this message]
2017-03-17 16:08 ` [PATCH v2 1/9] x86/cpuid: Sort cpu_has_* predicates by feature number Jan Beulich
2017-03-16 16:31 ` [PATCH v2 2/9] x86/pagewalk: Use pointer syntax for pfec parameter Andrew Cooper
2017-03-17 16:09 ` Jan Beulich
2017-03-20 11:29 ` George Dunlap
2017-03-23 16:28 ` Tim Deegan
2017-03-16 16:31 ` [PATCH v2 3/9] x86/shadow: Drop VALID_GFN() Andrew Cooper
2017-03-23 16:30 ` Tim Deegan
2017-03-16 16:31 ` [PATCH v2 4/9] x86/pagewalk: Clean up guest_supports_* predicates Andrew Cooper
2017-03-20 8:45 ` Jan Beulich
2017-03-20 13:36 ` Andrew Cooper
2017-03-20 13:59 ` Jan Beulich
2017-03-23 17:32 ` Andrew Cooper
2017-03-24 7:19 ` Jan Beulich
2017-03-23 16:34 ` Tim Deegan
2017-03-16 16:31 ` [PATCH v2 5/9] x86/pagewalk: Helpers for reserved bit handling Andrew Cooper
2017-03-20 8:48 ` Jan Beulich
2017-03-23 16:55 ` Tim Deegan
2017-03-23 17:02 ` Andrew Cooper
2017-03-23 17:12 ` Tim Deegan
2017-03-23 17:35 ` Andrew Cooper
2017-03-24 5:45 ` Juergen Gross
2017-03-24 7:51 ` Jan Beulich
[not found] ` <58D4DDFF0200007800147138@suse.com>
2017-03-24 7:58 ` Juergen Gross
2017-03-24 8:25 ` Jan Beulich
2017-03-24 9:06 ` Andrew Cooper
2017-03-24 7:47 ` Jan Beulich
2017-03-24 8:36 ` Andrew Cooper
2017-03-16 16:31 ` [PATCH v2 6/9] x86/pagewalk: Re-implement the pagetable walker Andrew Cooper
2017-03-16 16:31 ` [PATCH v2 7/9] x86/shadow: Use the pagewalk reserved bits helpers Andrew Cooper
2017-03-16 17:25 ` Andrew Cooper
2017-03-20 8:53 ` Jan Beulich
2017-03-23 16:57 ` Tim Deegan
2017-03-16 16:31 ` [PATCH v2 8/9] x86/pagewalk: Improve the logic behind setting access and dirty bits Andrew Cooper
2017-03-20 9:03 ` Jan Beulich
2017-03-23 17:09 ` Tim Deegan
2017-03-23 17:40 ` Andrew Cooper
2017-03-16 16:31 ` [PATCH v2 9/9] x86/pagewalk: non-functional cleanup Andrew Cooper
2017-03-20 9:04 ` Jan Beulich
2017-03-23 17:10 ` Tim Deegan
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