From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
he.chen@linux.intel.com, ian.jackson@eu.citrix.com,
Yi Sun <yi.y.sun@linux.intel.com>,
mengxu@cis.upenn.edu, jbeulich@suse.com,
chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: [PATCH v10 14/25] x86: refactor psr: CDP: implement CPU init and free flow.
Date: Sat, 1 Apr 2017 21:53:45 +0800 [thread overview]
Message-ID: <1491054836-30488-15-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1491054836-30488-1-git-send-email-yi.y.sun@linux.intel.com>
This patch implements the CPU init and free flow for CDP including L3 CDP
initialization callback function. The flow is almost same as L3 CAT.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v10:
- fix comment.
(suggested by Jan Beulich)
- use swith in 'cat_init_feature' to handle different feature types.
(suggested by Jan Beulich)
- changes about 'props'.
(suggested by Jan Beulich)
- restore MSRs to default value when cpu online.
(suggested by Jan Beulich)
- remove feat_mask.
(suggested by Jan Beulich)
v9:
- modify commit message to describe flow clearer.
- handle cpu offline and online again case to read MSRs registers values
back and save them into cos array to make user can get real data.
- modify error handling process in 'psr_cpu_prepare' to reduce redundant
codes.
- modify 'get_cdp_data' and 'get_cdp_code' to make them standard.
(suggested by Roger Pau and Jan Beulich)
- encapsulate CDP operations into 'cat_init_feature' to reduce redundant
codes.
(suggested by Roger Pau)
- reuse 'cat_get_cos_max' for CDP.
(suggested by Roger Pau)
- handle 'PSR_CDP' in psr_presmp_init to make init work can be done when
there is only 'psr=cdp' in cmdline.
- remove unnecessary comment.
(suggested by Jan Beulich)
- move CDP related codes in 'cpu_init_work' into 'psr_cpu_init'.
(suggested by Jan Beulich)
- add codes to handle CDP's 'cos_num'.
(suggested by Jan Beulich)
- fix coding style issue.
(suggested by Jan Beulich)
- do not free resources when allocation fails in 'psr_cpu_prepare'.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v7:
- initialize 'l3_cdp'.
(suggested by Konrad Rzeszutek Wilk)
v6:
- use 'cpuid_leaf'.
(suggested by Konrad Rzeszutek Wilk and Jan Beulich)
v5:
- remove codes to free 'feat_l3_cdp' in 'free_feature'.
(suggested by Jan Beulich)
- encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
(suggested by Jan Beulich)
- print socket info when 'opt_cpu_info' is true.
(suggested by Jan Beulich)
- rename 'l3_cdp_get_max_cos_max' to 'l3_cdp_get_cos_max'.
(suggested by Jan Beulich)
- rename 'dat[]' to 'data[]'.
(suggested by Jan Beulich)
- move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 76 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 0f57676..58970fa 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -144,11 +144,28 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
* array creation. It is used to transiently store a spare node.
*/
static struct feat_node *feat_l3_cat;
+static struct feat_node *feat_l3_cdp;
/* Common functions */
#define cat_default_val(len) (0xffffffff >> (32 - (len)))
/*
+ * get_cdp_data - get DATA COS register value from input COS ID.
+ * @feat: the feature node.
+ * @cos: the COS ID.
+ */
+#define get_cdp_data(feat, cos) \
+ ( (feat)->cos_reg_val[(cos) * 2] )
+
+/*
+ * get_cdp_code - get CODE COS register value from input COS ID.
+ * @feat: the feature node.
+ * @cos: the COS ID.
+ */
+#define get_cdp_code(feat, cos) \
+ ( (feat)->cos_reg_val[(cos) * 2 + 1] )
+
+/*
* Use this function to check if any allocation feature has been enabled
* in cmdline.
*/
@@ -283,6 +300,37 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
break;
+ case PSR_SOCKET_L3_CDP:
+ {
+ unsigned long val;
+
+ /* Cut half of cos_max when CDP is enabled. */
+ feat->props->cos_max >>= 1;
+
+ /* We only write mask1 since mask0 is always all ones by default. */
+ wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->props->cbm_len));
+ rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
+ wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT));
+
+ /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
+ get_cdp_code(feat, 0) = cat_default_val(feat->props->cbm_len);
+ get_cdp_data(feat, 0) = cat_default_val(feat->props->cbm_len);
+
+ /*
+ * To handle cpu offline and then online case, we need restore MSRs to
+ * default values.
+ */
+ for ( i = 1; i <= feat->props->cos_max; i++ )
+ {
+ wrmsrl(MSR_IA32_PSR_L3_MASK_DATA(i), get_cdp_data(feat, 0));
+ wrmsrl(MSR_IA32_PSR_L3_MASK_CODE(i), get_cdp_code(feat, 0));
+ get_cdp_code(feat, i) = get_cdp_code(feat, 0);
+ get_cdp_data(feat, i) = get_cdp_data(feat, 0);
+ }
+
+ break;
+ }
+
default:
return;
}
@@ -294,8 +342,9 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
if ( !opt_cpu_info )
return;
- printk(XENLOG_INFO "%s CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
- ((type == PSR_SOCKET_L3_CAT) ? "L3" : "L2"),
+ printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
+ ((type == PSR_SOCKET_L3_CDP) ? "CDP" :
+ ((type == PSR_SOCKET_L3_CAT) ? "L3 CAT": "L2 CAT")),
socket, feat->props->cos_max, feat->props->cbm_len);
}
@@ -336,6 +385,11 @@ static struct feat_props l3_cat_props = {
.write_msr = l3_cat_write_msr,
};
+/* L3 CDP ops */
+static struct feat_props l3_cdp_props = {
+ .cos_num = 2,
+};
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -1161,6 +1215,10 @@ static int psr_cpu_prepare(void)
(feat_l3_cat = xzalloc(struct feat_node)) == NULL )
return -ENOMEM;
+ if ( feat_l3_cdp == NULL &&
+ (feat_l3_cdp = xzalloc(struct feat_node)) == NULL )
+ return -ENOMEM;
+
return 0;
}
@@ -1193,11 +1251,21 @@ static void psr_cpu_init(void)
{
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s);
- feat = feat_l3_cat;
- feat_l3_cat = NULL;
- feat->props = &l3_cat_props;
-
- cat_init_feature(®s, feat, info, PSR_SOCKET_L3_CAT);
+ if ( (regs.c & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) &&
+ !info->features[PSR_SOCKET_L3_CDP] )
+ {
+ feat = feat_l3_cdp;
+ feat_l3_cdp = NULL;
+ feat->props = &l3_cdp_props;
+ cat_init_feature(®s, feat, info, PSR_SOCKET_L3_CDP);
+ }
+ else
+ {
+ feat = feat_l3_cat;
+ feat_l3_cat = NULL;
+ feat->props = &l3_cat_props;
+ cat_init_feature(®s, feat, info, PSR_SOCKET_L3_CAT);
+ }
}
assoc_init:
@@ -1257,7 +1325,7 @@ static int __init psr_presmp_init(void)
if ( (opt_psr & PSR_CMT) && opt_rmid_max )
init_psr_cmt(opt_rmid_max);
- if ( opt_psr & PSR_CAT )
+ if ( opt_psr & (PSR_CAT | PSR_CDP) )
init_psr();
if ( psr_cpu_prepare() )
--
1.9.1
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next prev parent reply other threads:[~2017-04-01 13:54 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-01 13:53 [PATCH v10 00/25] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-04-01 13:53 ` [PATCH v10 01/25] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-04-01 13:53 ` [PATCH v10 02/25] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-04-01 13:53 ` [PATCH v10 03/25] x86: refactor psr: implement main data structures Yi Sun
2017-04-03 15:50 ` Jan Beulich
2017-04-05 3:12 ` Yi Sun
2017-04-05 8:20 ` Jan Beulich
2017-04-05 8:45 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 04/25] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-04-01 13:53 ` [PATCH v10 05/25] x86: refactor psr: L3 CAT: implement CPU init and free flow Yi Sun
2017-04-05 15:10 ` Jan Beulich
2017-04-06 5:49 ` Yi Sun
2017-04-06 8:32 ` Jan Beulich
2017-04-06 9:22 ` Yi Sun
2017-04-06 9:34 ` Jan Beulich
2017-04-06 10:02 ` Yi Sun
2017-04-06 14:02 ` Jan Beulich
2017-04-07 5:17 ` Yi Sun
2017-04-07 8:48 ` Jan Beulich
2017-04-07 9:08 ` Yi Sun
2017-04-07 9:46 ` Jan Beulich
2017-04-10 3:27 ` Yi Sun
2017-04-10 12:43 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 06/25] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-04-05 15:23 ` Jan Beulich
2017-04-06 6:01 ` Yi Sun
2017-04-06 8:34 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 07/25] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-04-05 15:37 ` Jan Beulich
2017-04-06 6:05 ` Yi Sun
2017-04-06 8:36 ` Jan Beulich
2017-04-06 11:16 ` Yi Sun
2017-04-06 14:04 ` Jan Beulich
2017-04-07 5:39 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 08/25] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-04-05 15:51 ` Jan Beulich
2017-04-06 6:10 ` Yi Sun
2017-04-06 8:40 ` Jan Beulich
2017-04-06 11:13 ` Yi Sun
2017-04-06 14:08 ` Jan Beulich
2017-04-07 5:40 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 09/25] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-04-11 15:01 ` Jan Beulich
2017-04-12 5:53 ` Yi Sun
2017-04-12 9:09 ` Jan Beulich
2017-04-12 12:23 ` Yi Sun
2017-04-12 12:42 ` Jan Beulich
2017-04-13 8:11 ` Yi Sun
2017-04-13 9:41 ` Jan Beulich
2017-04-13 10:49 ` Yi Sun
2017-04-13 10:58 ` Jan Beulich
2017-04-13 11:11 ` Yi Sun
2017-04-13 11:26 ` Yi Sun
2017-04-13 11:31 ` Jan Beulich
2017-04-13 11:44 ` Yi Sun
2017-04-13 11:50 ` Jan Beulich
2017-04-18 10:55 ` Yi Sun
2017-04-18 11:46 ` Jan Beulich
2017-04-19 8:22 ` Yi Sun
2017-04-19 9:00 ` Jan Beulich
2017-04-20 2:14 ` Yi Sun
2017-04-20 9:43 ` Jan Beulich
2017-04-20 13:02 ` Lars Kurth
2017-04-20 13:21 ` Jan Beulich
2017-04-20 16:52 ` Lars Kurth
2017-04-21 6:11 ` Jan Beulich
2017-04-21 1:13 ` Konrad Rzeszutek Wilk
2017-04-21 6:18 ` Jan Beulich
2017-04-24 6:40 ` Yi Sun
2017-04-24 6:55 ` Jan Beulich
2017-04-25 7:15 ` Yi Sun
2017-04-25 8:24 ` Jan Beulich
2017-04-25 8:40 ` Yi Sun
2017-04-20 5:38 ` [PATCH] dom_ids array implementation Yi Sun
2017-04-26 10:04 ` Jan Beulich
2017-04-27 2:38 ` Yi Sun
2017-04-27 6:48 ` Jan Beulich
2017-04-27 9:30 ` Yi Sun
2017-04-27 9:39 ` Jan Beulich
2017-04-27 12:03 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 10/25] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-04-11 15:11 ` Jan Beulich
2017-04-12 5:55 ` Yi Sun
2017-04-12 9:13 ` Jan Beulich
2017-04-12 12:26 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 11/25] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-04-11 15:17 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 12/25] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-04-11 15:20 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 13/25] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-04-11 15:25 ` Jan Beulich
2017-04-12 6:04 ` Yi Sun
2017-04-01 13:53 ` Yi Sun [this message]
2017-04-01 13:53 ` [PATCH v10 15/25] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 16/25] x86: refactor psr: CDP: implement get value flow Yi Sun
2017-04-11 15:39 ` Jan Beulich
2017-04-12 6:05 ` Yi Sun
2017-04-12 9:14 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 17/25] x86: refactor psr: CDP: implement set value callback functions Yi Sun
2017-04-11 16:03 ` Jan Beulich
2017-04-12 6:14 ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 18/25] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-04-12 15:18 ` Jan Beulich
2017-04-13 8:12 ` Yi Sun
2017-04-13 8:16 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 19/25] x86: L2 CAT: implement get hw info flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 20/25] x86: L2 CAT: implement get value flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 21/25] x86: L2 CAT: implement set " Yi Sun
2017-04-12 15:23 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 22/25] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-04-12 15:24 ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 23/25] tools: L2 CAT: support show cbm " Yi Sun
2017-04-01 13:53 ` [PATCH v10 24/25] tools: L2 CAT: support set " Yi Sun
2017-04-01 13:53 ` [PATCH v10 25/25] docs: add L2 CAT description in docs Yi Sun
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