* [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h
@ 2017-06-06 10:01 Bhupinder Thakur
0 siblings, 0 replies; 3+ messages in thread
From: Bhupinder Thakur @ 2017-06-06 10:01 UTC (permalink / raw)
To: xen-devel; +Cc: Julien Grall, Stefano Stabellini
These functions are generic in nature and can be reused by other emulation
code in Xen. One recent example is pl011 emulation, which needs similar
functions to read/write the registers.
This patch moves the register access function definitions from vgic.h to
vreg.h.
Signed-off-by: Bhupinder Thakur <bhupinder.thakur@linaro.org>
---
Changes since v3:
- Moved the macro call VGIC_REG_HELPERS to vreg.h from vgic.h.
xen/include/asm-arm/vgic.h | 111 +--------------------------------------------
xen/include/asm-arm/vreg.h | 110 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 111 insertions(+), 110 deletions(-)
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 544867a..75c716e 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -20,6 +20,7 @@
#include <xen/bitops.h>
#include <asm/mmio.h>
+#include <asm-arm/vreg.h>
struct pending_irq
{
@@ -171,116 +172,6 @@ static inline int REG_RANK_NR(int b, uint32_t n)
}
}
-#define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8)))
-
-/*
- * The check on the size supported by the register has to be done by
- * the caller of vgic_regN_*.
- *
- * vgic_reg_* should never be called directly. Instead use the vgic_regN_*
- * according to size of the emulated register
- *
- * Note that the alignment fault will always be taken in the guest
- * (see B3.12.7 DDI0406.b).
- */
-static inline register_t vgic_reg_extract(unsigned long reg,
- unsigned int offset,
- enum dabt_size size)
-{
- reg >>= 8 * offset;
- reg &= VGIC_REG_MASK(size);
-
- return reg;
-}
-
-static inline void vgic_reg_update(unsigned long *reg, register_t val,
- unsigned int offset,
- enum dabt_size size)
-{
- unsigned long mask = VGIC_REG_MASK(size);
- int shift = offset * 8;
-
- *reg &= ~(mask << shift);
- *reg |= ((unsigned long)val & mask) << shift;
-}
-
-static inline void vgic_reg_setbits(unsigned long *reg, register_t bits,
- unsigned int offset,
- enum dabt_size size)
-{
- unsigned long mask = VGIC_REG_MASK(size);
- int shift = offset * 8;
-
- *reg |= ((unsigned long)bits & mask) << shift;
-}
-
-static inline void vgic_reg_clearbits(unsigned long *reg, register_t bits,
- unsigned int offset,
- enum dabt_size size)
-{
- unsigned long mask = VGIC_REG_MASK(size);
- int shift = offset * 8;
-
- *reg &= ~(((unsigned long)bits & mask) << shift);
-}
-
-/* N-bit register helpers */
-#define VGIC_REG_HELPERS(sz, offmask) \
-static inline register_t vgic_reg##sz##_extract(uint##sz##_t reg, \
- const mmio_info_t *info)\
-{ \
- return vgic_reg_extract(reg, info->gpa & offmask, \
- info->dabt.size); \
-} \
- \
-static inline void vgic_reg##sz##_update(uint##sz##_t *reg, \
- register_t val, \
- const mmio_info_t *info) \
-{ \
- unsigned long tmp = *reg; \
- \
- vgic_reg_update(&tmp, val, info->gpa & offmask, \
- info->dabt.size); \
- \
- *reg = tmp; \
-} \
- \
-static inline void vgic_reg##sz##_setbits(uint##sz##_t *reg, \
- register_t bits, \
- const mmio_info_t *info) \
-{ \
- unsigned long tmp = *reg; \
- \
- vgic_reg_setbits(&tmp, bits, info->gpa & offmask, \
- info->dabt.size); \
- \
- *reg = tmp; \
-} \
- \
-static inline void vgic_reg##sz##_clearbits(uint##sz##_t *reg, \
- register_t bits, \
- const mmio_info_t *info) \
-{ \
- unsigned long tmp = *reg; \
- \
- vgic_reg_clearbits(&tmp, bits, info->gpa & offmask, \
- info->dabt.size); \
- \
- *reg = tmp; \
-}
-
-/*
- * 64 bits registers are only supported on platform with 64-bit long.
- * This is also allow us to optimize the 32 bit case by using
- * unsigned long rather than uint64_t
- */
-#if BITS_PER_LONG == 64
-VGIC_REG_HELPERS(64, 0x7);
-#endif
-VGIC_REG_HELPERS(32, 0x3);
-
-#undef VGIC_REG_HELPERS
-
enum gic_sgi_mode;
/*
diff --git a/xen/include/asm-arm/vreg.h b/xen/include/asm-arm/vreg.h
index ed2bd6f..348584f 100644
--- a/xen/include/asm-arm/vreg.h
+++ b/xen/include/asm-arm/vreg.h
@@ -107,4 +107,114 @@ static inline bool vreg_emulate_sysreg64(struct cpu_user_regs *regs, union hsr h
#endif
+#define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8)))
+
+/*
+ * The check on the size supported by the register has to be done by
+ * the caller of vgic_regN_*.
+ *
+ * vgic_reg_* should never be called directly. Instead use the vgic_regN_*
+ * according to size of the emulated register
+ *
+ * Note that the alignment fault will always be taken in the guest
+ * (see B3.12.7 DDI0406.b).
+ */
+static inline register_t vgic_reg_extract(unsigned long reg,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ reg >>= 8 * offset;
+ reg &= VGIC_REG_MASK(size);
+
+ return reg;
+}
+
+static inline void vgic_reg_update(unsigned long *reg, register_t val,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ unsigned long mask = VGIC_REG_MASK(size);
+ int shift = offset * 8;
+
+ *reg &= ~(mask << shift);
+ *reg |= ((unsigned long)val & mask) << shift;
+}
+
+static inline void vgic_reg_setbits(unsigned long *reg, register_t bits,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ unsigned long mask = VGIC_REG_MASK(size);
+ int shift = offset * 8;
+
+ *reg |= ((unsigned long)bits & mask) << shift;
+}
+
+static inline void vgic_reg_clearbits(unsigned long *reg, register_t bits,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ unsigned long mask = VGIC_REG_MASK(size);
+ int shift = offset * 8;
+
+ *reg &= ~(((unsigned long)bits & mask) << shift);
+}
+
+/* N-bit register helpers */
+#define VGIC_REG_HELPERS(sz, offmask) \
+static inline register_t vgic_reg##sz##_extract(uint##sz##_t reg, \
+ const mmio_info_t *info)\
+{ \
+ return vgic_reg_extract(reg, info->gpa & offmask, \
+ info->dabt.size); \
+} \
+ \
+static inline void vgic_reg##sz##_update(uint##sz##_t *reg, \
+ register_t val, \
+ const mmio_info_t *info) \
+{ \
+ unsigned long tmp = *reg; \
+ \
+ vgic_reg_update(&tmp, val, info->gpa & offmask, \
+ info->dabt.size); \
+ \
+ *reg = tmp; \
+} \
+ \
+static inline void vgic_reg##sz##_setbits(uint##sz##_t *reg, \
+ register_t bits, \
+ const mmio_info_t *info) \
+{ \
+ unsigned long tmp = *reg; \
+ \
+ vgic_reg_setbits(&tmp, bits, info->gpa & offmask, \
+ info->dabt.size); \
+ \
+ *reg = tmp; \
+} \
+ \
+static inline void vgic_reg##sz##_clearbits(uint##sz##_t *reg, \
+ register_t bits, \
+ const mmio_info_t *info) \
+{ \
+ unsigned long tmp = *reg; \
+ \
+ vgic_reg_clearbits(&tmp, bits, info->gpa & offmask, \
+ info->dabt.size); \
+ \
+ *reg = tmp; \
+}
+
+/*
+ * 64 bits registers are only supported on platform with 64-bit long.
+ * This is also allow us to optimize the 32 bit case by using
+ * unsigned long rather than uint64_t
+ */
+#if BITS_PER_LONG == 64
+VGIC_REG_HELPERS(64, 0x7);
+#endif
+VGIC_REG_HELPERS(32, 0x3);
+
+#undef VGIC_REG_HELPERS
+
#endif /* __ASM_ARM_VREG__ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 00/14 v4] PL011 emulation support in Xen
@ 2017-06-06 17:25 Bhupinder Thakur
2017-06-06 17:25 ` [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h Bhupinder Thakur
0 siblings, 1 reply; 3+ messages in thread
From: Bhupinder Thakur @ 2017-06-06 17:25 UTC (permalink / raw)
To: xen-devel; +Cc: Wei Liu, Julien Grall, Stefano Stabellini, Ian Jackson
PL011 emulation for guests in Xen
===================================
Linaro has published VM System specification for ARM Processors, which
provides a set of guidelines for both guest OS and hypervisor implementations,
such that building OS images according to these guidelines guarantees
that those images can also run on hypervisors compliant with this specification.
One of the spec requirements is that the hypervisor must provide an
emulated PL011 UART as a serial console which meets the minimum requirements in
SBSA UART as defined in appendix B of the following
ARM Server Base Architecture Document:
https://static.docs.arm.com/den0029/a/Server_Base_System_Architecture_v3_1_ARM_DEN_0029A.pdf.
This feature allows the Xen guests to use SBSA compliant pl011 UART as
as a console.
Note that SBSA pl011 UART is a subset of full featured ARM pl011 UART and
supports only a subset of registers as mentioned below. It does not support
rx/tx DMA.
Currently, Xen supports paravirtualized (aka PV console) and an emulated serial
consoles. This feature will expose an emulated SBSA pl011 UART console to the
guest, which a user can access using xenconsole.
The device tree passed to the guest VM will contain the pl011 MMIO address
range and an irq for receiving rx/tx pl011 interrupts. The device tree format
is specified in Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt.
The Xen hypervisor will expose two types of interfaces to the backend and domU.
The interface exposed to domU will be an emulated pl011 UART by emulating the
access to the following pl011 registers by the guest.
- Data register (DR) - RW
- Raw interrupt status register (RIS) - RO
- Masked interrupt status register (MIS)- RO
- Interrupt Mask (IMSC) - RW
- Interrupt Clear (ICR) - WO
It will also inject the pl011 interrupts to the guest in the following
conditions:
- incoming data in the rx buffer for the guest
- there is space in the tx buffer for the guest to write more data
The interface exposed to the backend will be the same PV console interface,
which minimizes the changes required in xenconsole to support a new pl011 console.
This interface has rx and tx ring buffers and an event channel for
sending/receiving events from the backend.
So essentially Xen handles the data on behalf of domU and the backend. Any data
written by domU is captured by Xen and written to the TX (OUT) ring buffer
and a pl011 event is raised to the backend to read the TX ring buffer.
Similarly on reciving a pl011 event, Xen injects an interrupt to guest to
indicate there is data available in the RX (IN) ring buffer.
The pl011 UART state is completely captured in the set of registers
mentioned above and this state is updated everytime there is an event from
the backend or there is register read/write access from domU.
For example, if domU has masked the rx interrupt in the IMSC register, then Xen
will not inject an interrupt to guest and will just update the RIS register.
Once the interrupt is unmasked by guest, the interrupt will be delivered to the
guest.
Changes summary:
Xen Hypervisor
===============
1. Add emulation code to emulate read/write access to pl011 registers and pl011
interrupts:
- It emulates DR read/write by reading and writing from/to the IN and
OUT ring buffers and raising an event to dom0 when there is data in
the OUT ring buffer and injecting an interrupt to the guest when there
is data in the IN ring buffer.
- Other registers are related to interrupt management and essentially
control when interrupts are delivered to the guest.
2. Add a new domctl API to initialize vpl011 emulation in Xen.
3. Enable vpl011 emulation for a domain based on a libxl option passed during
domain creation.
Toolstack
==========
1. Add a new option "vuart" in the domU configuration file to enable/disable vuart.
2. Create a SBSA UART DT node in the guest device tree. It uses a fixed
vpl011 SPI IRQ number and MMIO address.
3. Call vpl011 init DOMCTL API to enable vpl011 emulation.
5. Add a new vuart xenstore node, which contains:
- ring-ref
- event channel
- buffer limit
- type
Xenconsoled
============
1. Split the domain structure to support multiple consoles.
2. Modify different APIs such as buffer_append() etc. to operate on the
console structure.
3. Add support for handling multiple consoles.
4. Add support for vuart console:
The vpl011 changes available at the following repo:
url: ssh://git@git.linaro.org:/people/bhupinder.thakur/xen.git
branch: vpl011_v4
There are some TBD items which need to be looked at in the future:
1. Currently UEFI firmware logs the output to hvc console only. How can
UEFI firmware be made aware of pl011 console and how it can use it
as a console instead of hvc.
2. Linux seems to have hvc console as the default console i.e. if no
console is specified then it uses hvc as the console. How can an
option be provided in Linux to select either hvc or pl011 as the
default console.
3. ACPI support for pl011 device.
CC: ij
CC: wl
CC: ss
CC: jg
CC: kw
Bhupinder Thakur (14):
xen/arm: vpl011: Move vgic register access functions to vreg.h
xen/arm: vpl011: Define generic vreg_reg* access functions in vreg.h
xen/arm: vpl011: Add pl011 uart emulation in Xen
xen/arm: vpl011: Add support for vuart in libxl
xen/arm: vpl011: Allocate a new GFN in the toolstack for vuart
xen/arm: vpl011: Add a new domctl API to initialize vpl011
xen/arm: vpl011: Add a new vuart node in the xenstore
xen/arm: vpl011: Modify xenconsole to define and use a new console
structure
xen/arm: vpl011: Modify xenconsole functions to take console structure
as input
xen/arm: vpl011: Modify xenconsole to support multiple consoles
xen/arm: vpl011: Add support for vuart console in xenconsole
xen/arm: vpl011: Add a new vuart console type to xenconsole client
xen/arm: vpl011: Add a pl011 uart DT node in the guest device tree
xen/arm: vpl011: Update documentation for vuart console support
config/arm32.mk | 1 +
config/arm64.mk | 1 +
docs/man/xl.cfg.pod.5.in | 9 +
docs/misc/console.txt | 44 ++-
tools/console/Makefile | 4 +-
tools/console/client/main.c | 25 +-
tools/console/daemon/io.c | 544 ++++++++++++++++++++++++-----------
tools/libxc/include/xc_dom.h | 3 +
tools/libxc/include/xenctrl.h | 17 ++
tools/libxc/xc_dom_arm.c | 12 +-
tools/libxc/xc_dom_boot.c | 2 +
tools/libxc/xc_domain.c | 23 ++
tools/libxl/libxl.h | 6 +
tools/libxl/libxl_arch.h | 7 +
tools/libxl/libxl_arm.c | 71 ++++-
tools/libxl/libxl_console.c | 47 +++
tools/libxl/libxl_create.c | 12 +-
tools/libxl/libxl_device.c | 9 +-
tools/libxl/libxl_dom.c | 8 +-
tools/libxl/libxl_internal.h | 7 +
tools/libxl/libxl_types.idl | 7 +
tools/libxl/libxl_types_internal.idl | 1 +
tools/libxl/libxl_x86.c | 8 +
tools/xl/Makefile | 4 +
tools/xl/xl_cmdtable.c | 4 +
tools/xl/xl_console.c | 11 +-
tools/xl/xl_parse.c | 8 +
xen/arch/arm/Kconfig | 5 +
xen/arch/arm/Makefile | 1 +
xen/arch/arm/domain.c | 2 +
xen/arch/arm/domctl.c | 44 ++-
xen/arch/arm/vgic-v2.c | 28 +-
xen/arch/arm/vgic-v3.c | 40 +--
xen/arch/arm/vpl011.c | 418 +++++++++++++++++++++++++++
xen/include/asm-arm/domain.h | 6 +
xen/include/asm-arm/pl011-uart.h | 2 +
xen/include/asm-arm/vgic.h | 111 +------
xen/include/asm-arm/vpl011.h | 74 +++++
xen/include/asm-arm/vreg.h | 109 +++++++
xen/include/public/arch-arm.h | 6 +
xen/include/public/domctl.h | 12 +
xen/include/public/io/console.h | 4 +
42 files changed, 1421 insertions(+), 336 deletions(-)
create mode 100644 xen/arch/arm/vpl011.c
create mode 100644 xen/include/asm-arm/vpl011.h
--
2.7.4
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^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h
2017-06-06 17:25 [PATCH 00/14 v4] PL011 emulation support in Xen Bhupinder Thakur
@ 2017-06-06 17:25 ` Bhupinder Thakur
2017-06-09 12:49 ` Julien Grall
0 siblings, 1 reply; 3+ messages in thread
From: Bhupinder Thakur @ 2017-06-06 17:25 UTC (permalink / raw)
To: xen-devel; +Cc: Julien Grall, Stefano Stabellini
These functions are generic in nature and can be reused by other emulation
code in Xen. One recent example is pl011 emulation, which needs similar
functions to read/write the registers.
This patch moves the register access function definitions from vgic.h to
vreg.h.
Signed-off-by: Bhupinder Thakur <bhupinder.thakur@linaro.org>
---
CC: ss
CC: jg
Changes since v3:
- Moved the macro call VGIC_REG_HELPERS to vreg.h from vgic.h.
xen/include/asm-arm/vgic.h | 111 +--------------------------------------------
xen/include/asm-arm/vreg.h | 110 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 111 insertions(+), 110 deletions(-)
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 544867a..75c716e 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -20,6 +20,7 @@
#include <xen/bitops.h>
#include <asm/mmio.h>
+#include <asm-arm/vreg.h>
struct pending_irq
{
@@ -171,116 +172,6 @@ static inline int REG_RANK_NR(int b, uint32_t n)
}
}
-#define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8)))
-
-/*
- * The check on the size supported by the register has to be done by
- * the caller of vgic_regN_*.
- *
- * vgic_reg_* should never be called directly. Instead use the vgic_regN_*
- * according to size of the emulated register
- *
- * Note that the alignment fault will always be taken in the guest
- * (see B3.12.7 DDI0406.b).
- */
-static inline register_t vgic_reg_extract(unsigned long reg,
- unsigned int offset,
- enum dabt_size size)
-{
- reg >>= 8 * offset;
- reg &= VGIC_REG_MASK(size);
-
- return reg;
-}
-
-static inline void vgic_reg_update(unsigned long *reg, register_t val,
- unsigned int offset,
- enum dabt_size size)
-{
- unsigned long mask = VGIC_REG_MASK(size);
- int shift = offset * 8;
-
- *reg &= ~(mask << shift);
- *reg |= ((unsigned long)val & mask) << shift;
-}
-
-static inline void vgic_reg_setbits(unsigned long *reg, register_t bits,
- unsigned int offset,
- enum dabt_size size)
-{
- unsigned long mask = VGIC_REG_MASK(size);
- int shift = offset * 8;
-
- *reg |= ((unsigned long)bits & mask) << shift;
-}
-
-static inline void vgic_reg_clearbits(unsigned long *reg, register_t bits,
- unsigned int offset,
- enum dabt_size size)
-{
- unsigned long mask = VGIC_REG_MASK(size);
- int shift = offset * 8;
-
- *reg &= ~(((unsigned long)bits & mask) << shift);
-}
-
-/* N-bit register helpers */
-#define VGIC_REG_HELPERS(sz, offmask) \
-static inline register_t vgic_reg##sz##_extract(uint##sz##_t reg, \
- const mmio_info_t *info)\
-{ \
- return vgic_reg_extract(reg, info->gpa & offmask, \
- info->dabt.size); \
-} \
- \
-static inline void vgic_reg##sz##_update(uint##sz##_t *reg, \
- register_t val, \
- const mmio_info_t *info) \
-{ \
- unsigned long tmp = *reg; \
- \
- vgic_reg_update(&tmp, val, info->gpa & offmask, \
- info->dabt.size); \
- \
- *reg = tmp; \
-} \
- \
-static inline void vgic_reg##sz##_setbits(uint##sz##_t *reg, \
- register_t bits, \
- const mmio_info_t *info) \
-{ \
- unsigned long tmp = *reg; \
- \
- vgic_reg_setbits(&tmp, bits, info->gpa & offmask, \
- info->dabt.size); \
- \
- *reg = tmp; \
-} \
- \
-static inline void vgic_reg##sz##_clearbits(uint##sz##_t *reg, \
- register_t bits, \
- const mmio_info_t *info) \
-{ \
- unsigned long tmp = *reg; \
- \
- vgic_reg_clearbits(&tmp, bits, info->gpa & offmask, \
- info->dabt.size); \
- \
- *reg = tmp; \
-}
-
-/*
- * 64 bits registers are only supported on platform with 64-bit long.
- * This is also allow us to optimize the 32 bit case by using
- * unsigned long rather than uint64_t
- */
-#if BITS_PER_LONG == 64
-VGIC_REG_HELPERS(64, 0x7);
-#endif
-VGIC_REG_HELPERS(32, 0x3);
-
-#undef VGIC_REG_HELPERS
-
enum gic_sgi_mode;
/*
diff --git a/xen/include/asm-arm/vreg.h b/xen/include/asm-arm/vreg.h
index ed2bd6f..348584f 100644
--- a/xen/include/asm-arm/vreg.h
+++ b/xen/include/asm-arm/vreg.h
@@ -107,4 +107,114 @@ static inline bool vreg_emulate_sysreg64(struct cpu_user_regs *regs, union hsr h
#endif
+#define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8)))
+
+/*
+ * The check on the size supported by the register has to be done by
+ * the caller of vgic_regN_*.
+ *
+ * vgic_reg_* should never be called directly. Instead use the vgic_regN_*
+ * according to size of the emulated register
+ *
+ * Note that the alignment fault will always be taken in the guest
+ * (see B3.12.7 DDI0406.b).
+ */
+static inline register_t vgic_reg_extract(unsigned long reg,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ reg >>= 8 * offset;
+ reg &= VGIC_REG_MASK(size);
+
+ return reg;
+}
+
+static inline void vgic_reg_update(unsigned long *reg, register_t val,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ unsigned long mask = VGIC_REG_MASK(size);
+ int shift = offset * 8;
+
+ *reg &= ~(mask << shift);
+ *reg |= ((unsigned long)val & mask) << shift;
+}
+
+static inline void vgic_reg_setbits(unsigned long *reg, register_t bits,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ unsigned long mask = VGIC_REG_MASK(size);
+ int shift = offset * 8;
+
+ *reg |= ((unsigned long)bits & mask) << shift;
+}
+
+static inline void vgic_reg_clearbits(unsigned long *reg, register_t bits,
+ unsigned int offset,
+ enum dabt_size size)
+{
+ unsigned long mask = VGIC_REG_MASK(size);
+ int shift = offset * 8;
+
+ *reg &= ~(((unsigned long)bits & mask) << shift);
+}
+
+/* N-bit register helpers */
+#define VGIC_REG_HELPERS(sz, offmask) \
+static inline register_t vgic_reg##sz##_extract(uint##sz##_t reg, \
+ const mmio_info_t *info)\
+{ \
+ return vgic_reg_extract(reg, info->gpa & offmask, \
+ info->dabt.size); \
+} \
+ \
+static inline void vgic_reg##sz##_update(uint##sz##_t *reg, \
+ register_t val, \
+ const mmio_info_t *info) \
+{ \
+ unsigned long tmp = *reg; \
+ \
+ vgic_reg_update(&tmp, val, info->gpa & offmask, \
+ info->dabt.size); \
+ \
+ *reg = tmp; \
+} \
+ \
+static inline void vgic_reg##sz##_setbits(uint##sz##_t *reg, \
+ register_t bits, \
+ const mmio_info_t *info) \
+{ \
+ unsigned long tmp = *reg; \
+ \
+ vgic_reg_setbits(&tmp, bits, info->gpa & offmask, \
+ info->dabt.size); \
+ \
+ *reg = tmp; \
+} \
+ \
+static inline void vgic_reg##sz##_clearbits(uint##sz##_t *reg, \
+ register_t bits, \
+ const mmio_info_t *info) \
+{ \
+ unsigned long tmp = *reg; \
+ \
+ vgic_reg_clearbits(&tmp, bits, info->gpa & offmask, \
+ info->dabt.size); \
+ \
+ *reg = tmp; \
+}
+
+/*
+ * 64 bits registers are only supported on platform with 64-bit long.
+ * This is also allow us to optimize the 32 bit case by using
+ * unsigned long rather than uint64_t
+ */
+#if BITS_PER_LONG == 64
+VGIC_REG_HELPERS(64, 0x7);
+#endif
+VGIC_REG_HELPERS(32, 0x3);
+
+#undef VGIC_REG_HELPERS
+
#endif /* __ASM_ARM_VREG__ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h
2017-06-06 17:25 ` [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h Bhupinder Thakur
@ 2017-06-09 12:49 ` Julien Grall
0 siblings, 0 replies; 3+ messages in thread
From: Julien Grall @ 2017-06-09 12:49 UTC (permalink / raw)
To: Bhupinder Thakur, xen-devel; +Cc: Stefano Stabellini
Hi Bhupinder,
On 06/06/17 18:25, Bhupinder Thakur wrote:
> These functions are generic in nature and can be reused by other emulation
> code in Xen. One recent example is pl011 emulation, which needs similar
> functions to read/write the registers.
>
> This patch moves the register access function definitions from vgic.h to
> vreg.h.
>
> Signed-off-by: Bhupinder Thakur <bhupinder.thakur@linaro.org>
> ---
> CC: ss
> CC: jg
>
> Changes since v3:
> - Moved the macro call VGIC_REG_HELPERS to vreg.h from vgic.h.
>
> xen/include/asm-arm/vgic.h | 111 +--------------------------------------------
> xen/include/asm-arm/vreg.h | 110 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 111 insertions(+), 110 deletions(-)
>
> diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
> index 544867a..75c716e 100644
> --- a/xen/include/asm-arm/vgic.h
> +++ b/xen/include/asm-arm/vgic.h
> @@ -20,6 +20,7 @@
>
> #include <xen/bitops.h>
> #include <asm/mmio.h>
> +#include <asm-arm/vreg.h>
You should include asm/vreg.h and not asm-arm/vreg.h. With that fixed:
Acked-by: Julien Grall <julien.grall@arm.com>
Cheers,
--
Julien Grall
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^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-06-09 12:49 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2017-06-06 10:01 [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h Bhupinder Thakur
-- strict thread matches above, loose matches on Subject: below --
2017-06-06 17:25 [PATCH 00/14 v4] PL011 emulation support in Xen Bhupinder Thakur
2017-06-06 17:25 ` [PATCH 01/14 v4] xen/arm: vpl011: Move vgic register access functions to vreg.h Bhupinder Thakur
2017-06-09 12:49 ` Julien Grall
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