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From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
	he.chen@linux.intel.com, ian.jackson@eu.citrix.com,
	Yi Sun <yi.y.sun@linux.intel.com>,
	mengxu@cis.upenn.edu, jbeulich@suse.com,
	chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: [PATCH v12 13/23] x86: refactor psr: CDP: implement CPU init flow.
Date: Wed, 14 Jun 2017 09:12:46 +0800	[thread overview]
Message-ID: <1497402776-22348-14-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1497402776-22348-1-git-send-email-yi.y.sun@linux.intel.com>

This patch implements the CPU init flow for CDP. The flow is almost
same as L3 CAT.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v12:
    - move 'type[]' assignment into l3_cdp_props declaration to make it be
      'const'.
      (suggested by Jan Beulich)
    - remove "L2 CAT" indication in printk.
      (suggested by Jan Beulich)
    - fix coding style issue.
      (suggested by Jan Beulich)
    - change 'val' type to uint64_t.
      (suggested by Jan Beulich)
    - use 1ull.
      (suggested by Jan Beulich)
    - restore mask(0) MSR to default value.
      (suggested by Jan Beulich)
v11:
    - changes about 'feat_props'.
      (suggested by Jan Beulich)
    - remove MSR restore action which is unnecessary.
      (suggested by Jan Beulich)
    - modify commit message.
v10:
    - fix comment.
      (suggested by Jan Beulich)
    - use swith in 'cat_init_feature' to handle different feature types.
      (suggested by Jan Beulich)
    - changes about 'props'.
      (suggested by Jan Beulich)
    - restore MSRs to default value when cpu online.
      (suggested by Jan Beulich)
    - remove feat_mask.
      (suggested by Jan Beulich)
v9:
    - modify commit message to describe flow clearer.
    - handle cpu offline and online again case to read MSRs registers values
      back and save them into cos array to make user can get real data.
    - modify error handling process in 'psr_cpu_prepare' to reduce redundant
      codes.
    - modify 'get_cdp_data' and 'get_cdp_code' to make them standard.
      (suggested by Roger Pau and Jan Beulich)
    - encapsulate CDP operations into 'cat_init_feature' to reduce redundant
      codes.
      (suggested by Roger Pau)
    - reuse 'cat_get_cos_max' for CDP.
      (suggested by Roger Pau)
    - handle 'PSR_CDP' in psr_presmp_init to make init work can be done when
      there is only 'psr=cdp' in cmdline.
    - remove unnecessary comment.
      (suggested by Jan Beulich)
    - move CDP related codes in 'cpu_init_work' into 'psr_cpu_init'.
      (suggested by Jan Beulich)
    - add codes to handle CDP's 'cos_num'.
      (suggested by Jan Beulich)
    - fix coding style issue.
      (suggested by Jan Beulich)
    - do not free resources when allocation fails in 'psr_cpu_prepare'.
      (suggested by Jan Beulich)
    - changes about 'uint64_t' to 'uint32_t'.
      (suggested by Jan Beulich)
v7:
    - initialize 'l3_cdp'.
      (suggested by Konrad Rzeszutek Wilk)
v6:
    - use 'cpuid_leaf'.
      (suggested by Konrad Rzeszutek Wilk and Jan Beulich)
v5:
    - remove codes to free 'feat_l3_cdp' in 'free_feature'.
      (suggested by Jan Beulich)
    - encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
      (suggested by Jan Beulich)
    - print socket info when 'opt_cpu_info' is true.
      (suggested by Jan Beulich)
    - rename 'l3_cdp_get_max_cos_max' to 'l3_cdp_get_cos_max'.
      (suggested by Jan Beulich)
    - rename 'dat[]' to 'data[]'.
      (suggested by Jan Beulich)
    - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
      (suggested by Jan Beulich)
v4:
    - create this patch to make codes easier to understand.
      (suggested by Jan Beulich)
---
---
 xen/arch/x86/psr.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 67 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 81d9a78..814f0e1 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -62,6 +62,7 @@
 
 enum psr_feat_type {
     PSR_SOCKET_L3_CAT,
+    PSR_SOCKET_L3_CDP,
     PSR_SOCKET_FEAT_NUM,
     PSR_SOCKET_FEAT_UNKNOWN,
 };
@@ -152,11 +153,28 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
  * array creation. It is used to transiently store a spare node.
  */
 static struct feat_node *feat_l3_cat;
+static struct feat_node *feat_l3_cdp;
 
 /* Common functions */
 #define cat_default_val(len) (0xffffffff >> (32 - (len)))
 
 /*
+ * get_cdp_data - get DATA COS register value from input COS ID.
+ * @feat:        the feature node.
+ * @cos:         the COS ID.
+ */
+#define get_cdp_data(feat, cos)              \
+            ((feat)->cos_reg_val[(cos) * 2])
+
+/*
+ * get_cdp_code - get CODE COS register value from input COS ID.
+ * @feat:        the feature node.
+ * @cos:         the COS ID.
+ */
+#define get_cdp_code(feat, cos)              \
+            ((feat)->cos_reg_val[(cos) * 2 + 1])
+
+/*
  * Use this function to check if any allocation feature has been enabled
  * in cmdline.
  */
@@ -253,6 +271,26 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
 
         break;
 
+    case PSR_SOCKET_L3_CDP:
+    {
+        uint64_t val;
+
+        /* Cut half of cos_max when CDP is enabled. */
+        feat->cos_max >>= 1;
+
+        wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len));
+        wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len));
+        rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
+        wrmsrl(MSR_IA32_PSR_L3_QOS_CFG,
+               val | (1ull << PSR_L3_QOS_CDP_ENABLE_BIT));
+
+        /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
+        get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len);
+        get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len);
+
+        break;
+    }
+
     default:
         return;
     }
@@ -263,7 +301,8 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
     if ( !opt_cpu_info )
         return;
 
-    printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
+    printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
+           ((type == PSR_SOCKET_L3_CDP) ? "CDP" : "L3 CAT"),
            cpu_to_socket(smp_processor_id()), feat->cos_max, feat->cbm_len);
 }
 
@@ -293,6 +332,13 @@ static const struct feat_props l3_cat_props = {
     .write_msr = l3_cat_write_msr,
 };
 
+/* L3 CDP props */
+static const struct feat_props l3_cdp_props = {
+    .cos_num = 2,
+    .type[0] = PSR_CBM_TYPE_L3_DATA,
+    .type[1] = PSR_CBM_TYPE_L3_CODE,
+};
+
 static void __init parse_psr_bool(char *s, char *value, char *feature,
                                   unsigned int mask)
 {
@@ -1263,6 +1309,10 @@ static int psr_cpu_prepare(void)
          (feat_l3_cat = xzalloc(struct feat_node)) == NULL )
         return -ENOMEM;
 
+    if ( feat_l3_cdp == NULL &&
+         (feat_l3_cdp = xzalloc(struct feat_node)) == NULL )
+        return -ENOMEM;
+
     return 0;
 }
 
@@ -1294,11 +1344,21 @@ static void psr_cpu_init(void)
     {
         cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, &regs);
 
-        feat = feat_l3_cat;
-        feat_l3_cat = NULL;
-        feat_props[PSR_SOCKET_L3_CAT] = &l3_cat_props;
-
-        cat_init_feature(&regs, feat, info, PSR_SOCKET_L3_CAT);
+        if ( (regs.c & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) &&
+             !info->features[PSR_SOCKET_L3_CDP] )
+        {
+            feat = feat_l3_cdp;
+            feat_l3_cdp = NULL;
+            feat_props[PSR_SOCKET_L3_CDP] = &l3_cdp_props;
+            cat_init_feature(&regs, feat, info, PSR_SOCKET_L3_CDP);
+        }
+        else
+        {
+            feat = feat_l3_cat;
+            feat_l3_cat = NULL;
+            feat_props[PSR_SOCKET_L3_CAT] = &l3_cat_props;
+            cat_init_feature(&regs, feat, info, PSR_SOCKET_L3_CAT);
+        }
 
         info->feat_init = true;
     }
@@ -1360,7 +1420,7 @@ static int __init psr_presmp_init(void)
     if ( (opt_psr & PSR_CMT) && opt_rmid_max )
         init_psr_cmt(opt_rmid_max);
 
-    if ( opt_psr & PSR_CAT )
+    if ( opt_psr & (PSR_CAT | PSR_CDP) )
         init_psr();
 
     if ( psr_cpu_prepare() )
-- 
1.9.1


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  parent reply	other threads:[~2017-06-14  1:25 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-14  1:12 [PATCH v12 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-06-14  1:12 ` [PATCH v12 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-06-14  1:12 ` [PATCH v12 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-06-14  1:12 ` [PATCH v12 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-06-14  1:12 ` [PATCH v12 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-06-28  7:12   ` Jan Beulich
2017-06-28  9:07     ` Yi Sun
2017-06-14  1:12 ` [PATCH v12 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-06-28  7:13   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-06-14  1:12 ` [PATCH v12 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-06-28  7:14   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-06-28  7:14   ` Jan Beulich
2017-06-28  9:09     ` Yi Sun
2017-06-28 11:43       ` Jan Beulich
2017-06-29  5:12         ` Yi Sun
2017-06-29  6:24           ` Jan Beulich
2017-06-29  7:21             ` Yi Sun
2017-06-14  1:12 ` [PATCH v12 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-06-29 17:56   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-06-29 17:57   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-06-29 17:59   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-06-29 18:00   ` Jan Beulich
2017-06-30  5:45     ` Yi Sun
2017-06-30  6:45       ` Jan Beulich
2017-06-30  7:08         ` Yi Sun
2017-06-14  1:12 ` Yi Sun [this message]
2017-06-30  6:40   ` [PATCH v12 13/23] x86: refactor psr: CDP: implement CPU init flow Jan Beulich
2017-06-30  6:59     ` Yi Sun
2017-06-30  7:33       ` Jan Beulich
2017-06-30  8:04         ` Yi Sun
2017-06-30  9:18           ` Jan Beulich
2017-07-04  1:40             ` Yi Sun
2017-07-04  7:28               ` Jan Beulich
2017-07-05  1:45                 ` Yi Sun
2017-06-14  1:12 ` [PATCH v12 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-06-30  6:41   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-06-30  6:42   ` Jan Beulich
2017-06-30  7:22     ` Yi Sun
2017-06-30  8:54       ` Yi Sun
2017-06-30  9:33         ` Jan Beulich
2017-06-30 11:29           ` Yi Sun
2017-06-30 12:02             ` Jan Beulich
2017-07-03  6:33               ` Yi Sun
2017-07-03  7:01                 ` Jan Beulich
2017-07-03  8:40                   ` Yi Sun
2017-07-03  9:18                     ` Jan Beulich
2017-07-03 12:52                       ` Yi Sun
2017-07-03 13:02                         ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-06-30  6:58   ` Jan Beulich
2017-06-30  7:27     ` Yi Sun
2017-06-30  7:36       ` Jan Beulich
2017-06-30  8:05         ` Yi Sun
2017-06-14  1:12 ` [PATCH v12 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-06-30  6:59   ` Jan Beulich
2017-06-14  1:12 ` [PATCH v12 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-06-14  1:12 ` [PATCH v12 19/23] x86: L2 CAT: implement set " Yi Sun
2017-06-14  1:12 ` [PATCH v12 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-06-14  1:12 ` [PATCH v12 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-06-14  1:12 ` [PATCH v12 22/23] tools: L2 CAT: support set " Yi Sun
2017-06-14  1:12 ` [PATCH v12 23/23] docs: add L2 CAT description in docs Yi Sun

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