From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
he.chen@linux.intel.com, ian.jackson@eu.citrix.com,
Yi Sun <yi.y.sun@linux.intel.com>,
mengxu@cis.upenn.edu, jbeulich@suse.com,
chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: [PATCH v12 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows.
Date: Wed, 14 Jun 2017 09:12:38 +0800 [thread overview]
Message-ID: <1497402776-22348-6-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1497402776-22348-1-git-send-email-yi.y.sun@linux.intel.com>
This patch implements the Domain init/free and schedule flows.
- When domain init, its psr resource should be allocated.
- When domain free, its psr resource should be freed too.
- When domain is scheduled, its COS ID on the socket should be
set into ASSOC register to make corresponding COS MSR value
work.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v12:
- fix coding style issue.
(suggested by Jan Beulich)
- in 'get_max_cos_max', invert the condition and dropping 'continue'.
(suggested by Jan Beulich)
- modify 'psr_assoc_cos' to directly return 'reg' value.
(suggested by Jan Beulich)
- modify code style.
(suggested by Jan Beulich)
- do not break domain creation if 'psr_cos_ids' allocation fails.
(suggested by Jan Beulich)
v11:
- replace 'feat_init_done()' to 'feat_init' flag.
(suggested by Jan Beulich)
- adjust parameters positions when calling 'psr_assoc_cos'.
(suggested by Jan Beulich)
- add comment to explain why to check 'psr_cos_ids'.
v10:
- remove 'cat_get_cos_max' as 'cos_max' is a feature property now which
can be directly used.
(suggested by Jan Beulich)
- replace 'info->feat_mask' check to 'feat_init_done'.
(suggested by Jan Beulich)
v9:
- rename 'l3_cat_get_cos_max' to 'cat_get_cos_max' to cover all CAT/CDP
features.
(suggested by Roger Pau)
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- implement 'psr_alloc_cos' to match 'psr_free_cos'.
(suggested by Wei Liu)
- use 'psr_alloc_feat_enabled'.
(suggested by Wei Liu)
- fix coding style issue.
(suggested by Wei Liu)
- remove 'inline'.
(suggested by Jan Beulich)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- remove 'psr_cos_ids' check in 'psr_free_cos'.
(suggested by Jan Beulich)
v6:
- change 'PSR_ASSOC_REG_POS' to 'PSR_ASSOC_REG_SHIFT'.
(suggested by Konrad Rzeszutek Wilk)
v5:
- rename 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
- define 'PSR_ASSOC_REG_POS'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
---
xen/arch/x86/domain.c | 3 +--
xen/arch/x86/psr.c | 67 ++++++++++++++++++++++++++++++++++++++++++++---
xen/include/asm-x86/psr.h | 2 +-
3 files changed, 65 insertions(+), 7 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 90e2b1f..a2abed1 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -646,8 +646,7 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags,
}
spin_lock_init(&d->arch.e820_lock);
- if ( (rc = psr_domain_init(d)) != 0 )
- goto fail;
+ psr_domain_init(d);
if ( is_hvm_domain(d) )
{
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 251746a..9fb0da8 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -50,6 +50,8 @@
*/
#define MAX_COS_REG_CNT 128
+#define PSR_ASSOC_REG_SHIFT 32
+
/*
* Every PSR feature uses some COS registers for each COS ID, e.g. CDP uses 2
* COS registers (DATA and CODE) for one COS ID, but CAT uses 1 COS register.
@@ -358,11 +360,37 @@ void psr_free_rmid(struct domain *d)
d->arch.psr_rmid = 0;
}
-static inline void psr_assoc_init(void)
+static unsigned int get_max_cos_max(const struct psr_socket_info *info)
+{
+ unsigned int cos_max = 0, i;
+
+ for ( i = 0; i < ARRAY_SIZE(info->features); i++ )
+ {
+ const struct feat_node *feat = info->features[i];
+
+ if ( feat )
+ cos_max = max(feat->cos_max, cos_max);
+ }
+
+ return cos_max;
+}
+
+static void psr_assoc_init(void)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
- if ( psr_cmt_enabled() )
+ if ( psr_alloc_feat_enabled() )
+ {
+ unsigned int socket = cpu_to_socket(smp_processor_id());
+ const struct psr_socket_info *info = socket_info + socket;
+ unsigned int cos_max = get_max_cos_max(info);
+
+ if ( info->feat_init )
+ psra->cos_mask = ((1ull << get_count_order(cos_max)) - 1) <<
+ PSR_ASSOC_REG_SHIFT;
+ }
+
+ if ( psr_cmt_enabled() || psra->cos_mask )
rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
}
@@ -371,6 +399,13 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned int rmid)
*reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
}
+static uint64_t psr_assoc_cos(uint64_t reg, unsigned int cos,
+ uint64_t cos_mask)
+{
+ return (reg & ~cos_mask) |
+ (((uint64_t)cos << PSR_ASSOC_REG_SHIFT) & cos_mask);
+}
+
void psr_ctxt_switch_to(struct domain *d)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
@@ -379,6 +414,14 @@ void psr_ctxt_switch_to(struct domain *d)
if ( psr_cmt_enabled() )
psr_assoc_rmid(®, d->arch.psr_rmid);
+ /* If domain's 'psr_cos_ids' is NULL, we set default value for it. */
+ if ( psra->cos_mask )
+ reg = psr_assoc_cos(reg,
+ (d->arch.psr_cos_ids ?
+ d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
+ 0),
+ psra->cos_mask);
+
if ( reg != psra->val )
{
wrmsrl(MSR_IA32_PSR_ASSOC, reg);
@@ -404,14 +447,30 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
return 0;
}
-int psr_domain_init(struct domain *d)
+/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
+static void psr_free_cos(struct domain *d)
{
- return 0;
+ xfree(d->arch.psr_cos_ids);
+ d->arch.psr_cos_ids = NULL;
+}
+
+static void psr_alloc_cos(struct domain *d)
+{
+ d->arch.psr_cos_ids = xzalloc_array(unsigned int, nr_sockets);
+ if ( !d->arch.psr_cos_ids )
+ printk(XENLOG_WARNING "Failed to alloc psr_cos_ids!\n");
+}
+
+void psr_domain_init(struct domain *d)
+{
+ if ( psr_alloc_feat_enabled() )
+ psr_alloc_cos(d);
}
void psr_domain_free(struct domain *d)
{
psr_free_rmid(d);
+ psr_free_cos(d);
}
static void __init init_psr(void)
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 57f47e9..d146706 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -70,7 +70,7 @@ int psr_get_l3_cbm(struct domain *d, unsigned int socket,
int psr_set_l3_cbm(struct domain *d, unsigned int socket,
uint64_t cbm, enum cbm_type type);
-int psr_domain_init(struct domain *d);
+void psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
#endif /* __ASM_PSR_H__ */
--
1.9.1
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next prev parent reply other threads:[~2017-06-14 1:25 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-14 1:12 [PATCH v12 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-06-14 1:12 ` [PATCH v12 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-06-14 1:12 ` [PATCH v12 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-06-14 1:12 ` [PATCH v12 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-06-14 1:12 ` [PATCH v12 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-06-28 7:12 ` Jan Beulich
2017-06-28 9:07 ` Yi Sun
2017-06-14 1:12 ` Yi Sun [this message]
2017-06-28 7:13 ` [PATCH v12 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Jan Beulich
2017-06-14 1:12 ` [PATCH v12 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-06-14 1:12 ` [PATCH v12 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-06-28 7:14 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-06-28 7:14 ` Jan Beulich
2017-06-28 9:09 ` Yi Sun
2017-06-28 11:43 ` Jan Beulich
2017-06-29 5:12 ` Yi Sun
2017-06-29 6:24 ` Jan Beulich
2017-06-29 7:21 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-06-29 17:56 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-06-29 17:57 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-06-29 17:59 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-06-29 18:00 ` Jan Beulich
2017-06-30 5:45 ` Yi Sun
2017-06-30 6:45 ` Jan Beulich
2017-06-30 7:08 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 13/23] x86: refactor psr: CDP: implement CPU init flow Yi Sun
2017-06-30 6:40 ` Jan Beulich
2017-06-30 6:59 ` Yi Sun
2017-06-30 7:33 ` Jan Beulich
2017-06-30 8:04 ` Yi Sun
2017-06-30 9:18 ` Jan Beulich
2017-07-04 1:40 ` Yi Sun
2017-07-04 7:28 ` Jan Beulich
2017-07-05 1:45 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-06-30 6:41 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-06-30 6:42 ` Jan Beulich
2017-06-30 7:22 ` Yi Sun
2017-06-30 8:54 ` Yi Sun
2017-06-30 9:33 ` Jan Beulich
2017-06-30 11:29 ` Yi Sun
2017-06-30 12:02 ` Jan Beulich
2017-07-03 6:33 ` Yi Sun
2017-07-03 7:01 ` Jan Beulich
2017-07-03 8:40 ` Yi Sun
2017-07-03 9:18 ` Jan Beulich
2017-07-03 12:52 ` Yi Sun
2017-07-03 13:02 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-06-30 6:58 ` Jan Beulich
2017-06-30 7:27 ` Yi Sun
2017-06-30 7:36 ` Jan Beulich
2017-06-30 8:05 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-06-30 6:59 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-06-14 1:12 ` [PATCH v12 19/23] x86: L2 CAT: implement set " Yi Sun
2017-06-14 1:12 ` [PATCH v12 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-06-14 1:12 ` [PATCH v12 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-06-14 1:12 ` [PATCH v12 22/23] tools: L2 CAT: support set " Yi Sun
2017-06-14 1:12 ` [PATCH v12 23/23] docs: add L2 CAT description in docs Yi Sun
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