[PATCH v15 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c

[Yi Sun <yi.y.sun@linux.intel.com>]

Hi all,

We plan to bring a new PSR (Platform Shared Resource) feature called
Intel L2 Cache Allocation Technology (L2 CAT) to Xen. It has been enabled
in Linux Kernel.

Besides the L2 CAT implementaion, we refactor the psr.c to make it more
flexible and easily to extend to add new features. We abstract the general
operations of all features and encapsulate them into a structure. Then,
the development of new feature is simple to mainly implement these callback
functions.

The patch set can be found at:
https://github.com/yisun-git/xen.git l2_cat_v15

---
Acked and Reviewed list before V15:
  The changes in some reviewed patches are small. So I retain the a/r.

a - Acked-by
r - Reviewed-by

  r  patch 1  - docs: create Cache Allocation Technology (CAT) and Code and
                Data Prioritization (CDP) feature document
  a  patch 2  - x86: move cpuid_count_leaf from cpuid.c to processor.h.
  ar patch 3  - x86: refactor psr: remove L3 CAT/CDP codes.
  r  patch 4  - x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows.
  r  patch 5  - x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows.
  r  patch 6  - x86: refactor psr: L3 CAT: implement get hw info flow.
  r  patch 7  - x86: refactor psr: L3 CAT: implement get value flow.
  r  patch 8  - x86: refactor psr: L3 CAT: set value: implement framework.
  r  patch 9  - x86: refactor psr: L3 CAT: set value: assemble features value array.
  r  patch 10 - x86: refactor psr: L3 CAT: set value: implement cos finding flow.
  r  patch 11 - x86: refactor psr: L3 CAT: set value: implement cos id picking flow.
  r  patch 12 - x86: refactor psr: L3 CAT: set value: implement write msr flow.
  r  patch 14 - x86: refactor psr: CDP: implement get hw info flow.
  r  patch 15 - x86: refactor psr: CDP: implement set value callback function.
  r  patch 16 - x86: L2 CAT: implement CPU init flow.
  r  patch 17 - x86: L2 CAT: implement get hw info flow.
  r  patch 18 - x86: L2 CAT: implement get value flow.
  r  patch 19 - x86: L2 CAT: implement set value flow.
  a  patch 20 - tools: L2 CAT: support get HW info for L2 CAT.
  a  patch 21 - tools: L2 CAT: support show cbm for L2 CAT.
  a  patch 22 - tools: L2 CAT: support set cbm for L2 CAT.
  a  patch 23 - docs: add L2 CAT description in docs.

---
V15 change list:

Patch 1:
    - add 'alt_type' in 'feat_props' structure.
Patch 9:
    - remove unnecessary 'else' in 'insert_val_into_array'.
      (suggested by Jan Beulich)
Patch 12:
    - remove unnecessary 'else' in 'write_psr_msrs'.
      (suggested by Jan Beulich)
Patch 13:
    - refine process in 'psr_cpu_init' to remove the 'goto'.
      (suggested by Jan Beulich)
Patch 16:
    - remove a blank.
      (suggested by Jan Beulich)
    - use designated initializers to initialize the 'cat_feat_name'.
      (suggested by Jan Beulich)

Yi Sun (23):
  docs: create Cache Allocation Technology (CAT) and Code and Data
    Prioritization (CDP) feature document
  x86: move cpuid_count_leaf from cpuid.c to processor.h.
  x86: refactor psr: remove L3 CAT/CDP codes.
  x86: refactor psr: L3 CAT: implement main data structures, CPU init
    and free flows.
  x86: refactor psr: L3 CAT: implement Domain init/free and schedule
    flows.
  x86: refactor psr: L3 CAT: implement get hw info flow.
  x86: refactor psr: L3 CAT: implement get value flow.
  x86: refactor psr: L3 CAT: set value: implement framework.
  x86: refactor psr: L3 CAT: set value: assemble features value array.
  x86: refactor psr: L3 CAT: set value: implement cos finding flow.
  x86: refactor psr: L3 CAT: set value: implement cos id picking flow.
  x86: refactor psr: L3 CAT: set value: implement write msr flow.
  x86: refactor psr: CDP: implement CPU init flow.
  x86: refactor psr: CDP: implement get hw info flow.
  x86: refactor psr: CDP: implement set value callback function.
  x86: L2 CAT: implement CPU init flow.
  x86: L2 CAT: implement get hw info flow.
  x86: L2 CAT: implement get value flow.
  x86: L2 CAT: implement set value flow.
  tools: L2 CAT: support get HW info for L2 CAT.
  tools: L2 CAT: support show cbm for L2 CAT.
  tools: L2 CAT: support set cbm for L2 CAT.
  docs: add L2 CAT description in docs.

 docs/features/intel_psr_cat_cdp.pandoc |  471 +++++++++++
 docs/man/xl.pod.1.in                   |   27 +-
 docs/misc/xl-psr.markdown              |   18 +-
 tools/libxc/include/xenctrl.h          |    7 +-
 tools/libxc/xc_psr.c                   |   45 +-
 tools/libxl/libxl.h                    |    9 +
 tools/libxl/libxl_psr.c                |   28 +-
 tools/libxl/libxl_types.idl            |    1 +
 tools/xl/xl_cmdtable.c                 |    6 +-
 tools/xl/xl_psr.c                      |  168 ++--
 xen/arch/x86/cpuid.c                   |    6 -
 xen/arch/x86/domain.c                  |    3 +-
 xen/arch/x86/domctl.c                  |   51 +-
 xen/arch/x86/psr.c                     | 1409 ++++++++++++++++++++++++--------
 xen/arch/x86/sysctl.c                  |   38 +-
 xen/include/asm-x86/msr-index.h        |    1 +
 xen/include/asm-x86/processor.h        |    7 +
 xen/include/asm-x86/psr.h              |   29 +-
 xen/include/public/domctl.h            |    2 +
 xen/include/public/sysctl.h            |    3 +-
 20 files changed, 1887 insertions(+), 442 deletions(-)
 create mode 100644 docs/features/intel_psr_cat_cdp.pandoc

-- 
1.9.1


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel