From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
ian.jackson@eu.citrix.com, Yi Sun <yi.y.sun@linux.intel.com>,
julien.grall@arm.com, mengxu@cis.upenn.edu, jbeulich@suse.com,
chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: [PATCH v1 13/13] docs: add MBA description in docs
Date: Wed, 9 Aug 2017 15:41:52 +0800 [thread overview]
Message-ID: <1502264512-4648-14-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1502264512-4648-1-git-send-email-yi.y.sun@linux.intel.com>
This patch adds MBA description in related documents.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
docs/man/xl.pod.1.in | 33 ++++++++++++++++++++++++++
docs/misc/xl-psr.markdown | 60 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 93 insertions(+)
diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 16c8306..61f5bcb 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1798,6 +1798,39 @@ processed.
=back
+=head2 Memory Bandwidth Allocation
+
+Intel Skylake and later server platforms offer capabilities to configure and
+make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
+OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
+control system via exposing control over a credit-based throttling mechanism.
+In the Xen implementation, MBA is used to control memory bandwidth on VM basis.
+To enforce bandwidth on a specific domain, just set throttling value (THRTL)
+for the domain.
+
+=over 4
+
+=item B<psr-mba-set> [I<OPTIONS>] I<domain-id> I<thrtl>
+
+Set throttling value (THRTL) for a domain. For how to specify I<thrtl>
+please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-s SOCKET>, B<--socket=SOCKET>
+
+Specify the socket to process, otherwise all sockets are processed.
+
+=back
+
+=item B<psr-mba-show> [I<domain-id>]
+
+Show MBA settings for a certain domain or all domains.
+
+=back
+
=head1 IGNORED FOR COMPATIBILITY WITH XM
xl is mostly command-line compatible with the old xm utility used with
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index 04dd957..59d93ef 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -186,6 +186,66 @@ Setting data CBM for a domain:
Setting the same code and data CBM for a domain:
`xl psr-cat-set <domid> <cbm>`
+## Memory Bandwidth Allocation (MBA)
+
+Memory Bandwidth Allocation (MBA) is a new feature available on Intel
+Skylake and later server platforms that allows an OS or Hypervisor/VMM to
+slow misbehaving apps/VMs or create advanced closed-loop control system via
+exposing control over a credit-based throttling mechanism. To enforce bandwidth
+on a specific domain, just set throttling value (THRTL) into Class of Service
+(COS). MBA provides two THRTL mode. One is linear mode and the other is
+non-linear mode.
+
+In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
+not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
+to 10% delay applied).
+
+If linear values are not supported then input delay values are powers-of-two
+from zero to the THRTL_MAX value from CPUID. In this case any values not a power
+of two will be rounded down the next nearest power of two.
+
+For example, assuming a system with 2 domains:
+
+ * A THRTL of 0x0 for every domain means each domain can access the whole cache
+ without any delay. This is the default.
+
+ * Linear mode: Giving one domain a THRTL of 0xC and the other domain's 0 means
+ that the first domain gets 10% delay to access the cache and the other one
+ without any delay.
+
+ * Non-linear mode: Giving one domain a THRTL of 0xC and the other domain's 0
+ means that the first domain gets 8% delay to access the cache and the other
+ one without any delay.
+
+For more detailed information please refer to Intel SDM chapter
+"Introduction to Memory Bandwidth Allocation".
+
+In Xen's implementation, THRTL can be configured with libxl/xl interfaces but
+COS is maintained in hypervisor only. The cache partition granularity is per
+domain, each domain has COS=0 assigned by default, the corresponding THRTL is
+0, which means all the cache resource can be accessed without delay.
+
+### xl interfaces
+
+System MBA information such as maximum COS and maximum THRTL can be obtained by:
+
+`xl psr-hwinfo --mba`
+
+The simplest way to change a domain's THRTL from its default is running:
+
+`xl psr-mba-set [OPTIONS] <domid> <thrtl>`
+
+In a multi-socket system, the same thrtl will be set on each socket by default.
+Per socket thrtl can be specified with the `--socket SOCKET` option.
+
+Setting the THRTL may not be successful if insufficient COS is available. In
+such case unused COS(es) may be freed by setting THRTL of all related domains to
+its default value(0).
+
+Per domain THRTL settings can be shown by:
+
+`xl psr-mba-show [OPTIONS] <domid>`
+
## Reference
[1] Intel SDM
--
1.9.1
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next prev parent reply other threads:[~2017-08-09 7:58 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-08-14 7:35 ` Chao Peng
2017-08-14 8:23 ` Yi Sun
2017-08-14 9:36 ` Chao Peng
2017-08-15 10:08 ` Wei Liu
2017-08-16 2:51 ` Yi Sun
2017-08-09 7:41 ` [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-08-15 10:12 ` Wei Liu
2017-08-16 2:48 ` Yi Sun
2017-08-15 14:03 ` Daniel De Graaf
2017-08-09 7:41 ` [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general Yi Sun
2017-08-15 10:13 ` Wei Liu
2017-08-16 2:17 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-08-15 10:50 ` Wei Liu
2017-08-16 7:18 ` Yi Sun
2017-08-17 9:49 ` Wei Liu
2017-08-16 3:14 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 05/13] x86: implement get hw info " Yi Sun
2017-08-16 3:23 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 06/13] x86: implement get value interface " Yi Sun
2017-08-16 6:38 ` Chao Peng
2017-08-16 6:43 ` Yi Sun
2017-08-17 7:51 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 07/13] x86: implement set value flow " Yi Sun
2017-08-18 3:32 ` Chao Peng
2017-08-18 9:25 ` Yi Sun
2017-08-21 7:54 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 08/13] tools: create general interfaces to support psr allocation features Yi Sun
2017-08-21 10:12 ` Chao Peng
2017-08-22 2:38 ` Yi Sun
2017-08-22 6:42 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all " Yi Sun
2017-08-15 11:14 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
2017-08-22 2:38 ` Yi Sun
2017-08-09 7:41 ` [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type' Yi Sun
2017-08-15 11:15 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features Yi Sun
2017-08-15 11:24 ` Wei Liu
2017-08-21 10:14 ` Chao Peng
2017-08-22 2:24 ` Yi Sun
2017-08-22 6:44 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 12/13] tools: implemet new set " Yi Sun
2017-08-15 11:25 ` Wei Liu
2017-08-21 10:15 ` Chao Peng
2017-08-09 7:41 ` Yi Sun [this message]
2017-08-15 11:26 ` [PATCH v1 13/13] docs: add MBA description in docs Wei Liu
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