From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
ian.jackson@eu.citrix.com, Yi Sun <yi.y.sun@linux.intel.com>,
julien.grall@arm.com, mengxu@cis.upenn.edu, jbeulich@suse.com,
chao.p.peng@linux.intel.com, dgdegra@tycho.nsa.gov,
roger.pau@citrix.com
Subject: [PATCH v3 15/15] docs: add MBA description in docs
Date: Tue, 5 Sep 2017 17:32:37 +0800 [thread overview]
Message-ID: <1504603957-5389-16-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1504603957-5389-1-git-send-email-yi.y.sun@linux.intel.com>
This patch adds MBA description in related documents.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
v2:
- state the value type shown by 'psr-mba-show'. For linear mode,
it shows decimal value. For non-linear mode, it shows hexadecimal
value.
(suggested by Chao Peng)
---
docs/man/xl.pod.1.in | 34 +++++++++++++++++++++++++
docs/misc/xl-psr.markdown | 63 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+)
diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 16c8306..e644b19 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1798,6 +1798,40 @@ processed.
=back
+=head2 Memory Bandwidth Allocation
+
+Intel Skylake and later server platforms offer capabilities to configure and
+make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
+OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
+control system via exposing control over a credit-based throttling mechanism.
+In the Xen implementation, MBA is used to control memory bandwidth on VM basis.
+To enforce bandwidth on a specific domain, just set throttling value (THRTL)
+for the domain.
+
+=over 4
+
+=item B<psr-mba-set> [I<OPTIONS>] I<domain-id> I<thrtl>
+
+Set throttling value (THRTL) for a domain. For how to specify I<thrtl>
+please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-s SOCKET>, B<--socket=SOCKET>
+
+Specify the socket to process, otherwise all sockets are processed.
+
+=back
+
+=item B<psr-mba-show> [I<domain-id>]
+
+Show MBA settings for a certain domain or all domains. For linear mode, it
+shows the decimal value. For non-linear mode, it shows hexadecimal value.
+
+=back
+
=head1 IGNORED FOR COMPATIBILITY WITH XM
xl is mostly command-line compatible with the old xm utility used with
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index 04dd957..39fc801 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -186,6 +186,69 @@ Setting data CBM for a domain:
Setting the same code and data CBM for a domain:
`xl psr-cat-set <domid> <cbm>`
+## Memory Bandwidth Allocation (MBA)
+
+Memory Bandwidth Allocation (MBA) is a new feature available on Intel
+Skylake and later server platforms that allows an OS or Hypervisor/VMM to
+slow misbehaving apps/VMs or create advanced closed-loop control system via
+exposing control over a credit-based throttling mechanism. To enforce bandwidth
+on a specific domain, just set throttling value (THRTL) into Class of Service
+(COS). MBA provides two THRTL mode. One is linear mode and the other is
+non-linear mode.
+
+In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
+not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
+to 10% delay applied).
+
+If linear values are not supported then input delay values are powers-of-two
+from zero to the THRTL_MAX value from CPUID. In this case any values not a power
+of two will be rounded down the next nearest power of two.
+
+For example, assuming a system with 2 domains:
+
+ * A THRTL of 0x0 for every domain means each domain can access the whole cache
+ without any delay. This is the default.
+
+ * Linear mode: Giving one domain a THRTL of 0xC and the other domain's 0 means
+ that the first domain gets 10% delay to access the cache and the other one
+ without any delay.
+
+ * Non-linear mode: Giving one domain a THRTL of 0xC and the other domain's 0
+ means that the first domain gets 8% delay to access the cache and the other
+ one without any delay.
+
+For more detailed information please refer to Intel SDM chapter
+"Introduction to Memory Bandwidth Allocation".
+
+In Xen's implementation, THRTL can be configured with libxl/xl interfaces but
+COS is maintained in hypervisor only. The cache partition granularity is per
+domain, each domain has COS=0 assigned by default, the corresponding THRTL is
+0, which means all the cache resource can be accessed without delay.
+
+### xl interfaces
+
+System MBA information such as maximum COS and maximum THRTL can be obtained by:
+
+`xl psr-hwinfo --mba`
+
+The simplest way to change a domain's THRTL from its default is running:
+
+`xl psr-mba-set [OPTIONS] <domid> <thrtl>`
+
+In a multi-socket system, the same thrtl will be set on each socket by default.
+Per socket thrtl can be specified with the `--socket SOCKET` option.
+
+Setting the THRTL may not be successful if insufficient COS is available. In
+such case unused COS(es) may be freed by setting THRTL of all related domains to
+its default value(0).
+
+Per domain THRTL settings can be shown by:
+
+`xl psr-mba-show [OPTIONS] <domid>`
+
+For linear mode, it shows the decimal value. For non-linear mode, it shows
+hexadecimal value.
+
## Reference
[1] Intel SDM
--
1.9.1
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next prev parent reply other threads:[~2017-09-05 9:52 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-09-05 9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-09-18 17:16 ` Roger Pau Monné
2017-09-19 6:07 ` Jan Beulich
2017-09-20 2:59 ` Yi Sun
2017-09-20 3:06 ` Yi Sun
2017-09-20 8:36 ` Roger Pau Monné
2017-09-20 9:08 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-09-19 8:03 ` Roger Pau Monné
2017-09-20 3:12 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
2017-09-19 8:22 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-09-19 8:55 ` Roger Pau Monné
2017-09-20 3:22 ` Yi Sun
2017-09-20 7:11 ` Jan Beulich
2017-09-20 7:27 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 05/15] x86: implement get hw info " Yi Sun
2017-09-19 9:08 ` Roger Pau Monné
2017-09-20 5:05 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 06/15] x86: implement get value interface " Yi Sun
2017-09-19 9:15 ` Roger Pau Monné
2017-09-20 5:09 ` Yi Sun
2017-09-20 8:43 ` Roger Pau Monné
2017-09-20 9:22 ` Yi Sun
2017-09-20 16:02 ` Wei Liu
2017-09-05 9:32 ` [PATCH v3 07/15] x86: implement set value flow " Yi Sun
2017-09-19 9:57 ` Roger Pau Monné
2017-09-20 5:39 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 08/15] tools: create general interfaces to support psr allocation features Yi Sun
2017-09-19 10:04 ` Roger Pau Monné
2017-09-20 5:45 ` Yi Sun
2017-09-22 7:01 ` Chao Peng
2017-09-28 16:11 ` Wei Liu
2017-09-05 9:32 ` [PATCH v3 09/15] tools: implement the new libxc get hw info interface Yi Sun
2017-09-19 10:15 ` Roger Pau Monné
2017-09-20 6:13 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 10/15] tools: implement the new libxl " Yi Sun
2017-09-19 10:28 ` Roger Pau Monné
2017-09-20 6:20 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 11/15] tools: implement the new xl " Yi Sun
2017-09-19 10:32 ` Roger Pau Monné
2017-09-20 6:23 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
2017-09-19 10:34 ` Roger Pau Monné
2017-09-20 6:25 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command Yi Sun
2017-09-19 11:02 ` Roger Pau Monné
2017-09-20 6:46 ` Yi Sun
2017-09-20 8:57 ` Roger Pau Monné
2017-09-20 9:11 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 14/15] tools: implement new generic set value interface and MBA set " Yi Sun
2017-09-19 11:30 ` Roger Pau Monné
2017-09-20 7:25 ` Yi Sun
2017-09-20 16:10 ` Wei Liu
2017-09-28 16:23 ` Dario Faggioli
2017-09-29 12:58 ` Wei Liu
2017-09-05 9:32 ` Yi Sun [this message]
2017-09-19 11:37 ` [PATCH v3 15/15] docs: add MBA description in docs Roger Pau Monné
2017-09-20 7:26 ` Yi Sun
2017-09-28 16:56 ` Dario Faggioli
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