From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dario Faggioli <dario.faggioli@citrix.com>
Subject: Re: [PATCH v2 4/5] xentrace: enable per-VCPU extratime
	flag for RTDS
Date: Thu, 14 Sep 2017 02:55:55 +0200
Message-ID: <1505350555.13935.8.camel@citrix.com>
References: <1504281532-3766-1-git-send-email-mengxu@cis.upenn.edu>
 <1504281532-3766-5-git-send-email-mengxu@cis.upenn.edu>
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On Fri, 2017-09-01 at 11:58 -0400, Meng Xu wrote:
> Change repl_budget event output for xentrace formats and xenalyze
>=20
> Signed-off-by: Meng Xu <mengxu@cis.upenn.edu>
>=20
Right, thanks for doing this part too. However, can you merge this
inside patch 1?

> diff --git a/tools/xentrace/formats b/tools/xentrace/formats
> index f39182a..470ac5c 100644
> --- a/tools/xentrace/formats
> +++ b/tools/xentrace/formats
> @@ -75,7 +75,7 @@
> =C2=A00x00022801=C2=A0=C2=A0CPU%(cpu)d=C2=A0=C2=A0%(tsc)d (+%(reltsc)8d)=
=C2=A0=C2=A0rtds:tickle=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0[ cp=
u =3D %(1)d ]
> =C2=A00x00022802=C2=A0=C2=A0CPU%(cpu)d=C2=A0=C2=A0%(tsc)d (+%(reltsc)8d)=
=C2=A0=C2=A0rtds:runq_pick=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0[ dom:vcpu =3D 0x%(=
1)08x, cur_deadline =3D 0x%(3)08x%(2)08x, cur_budget =3D 0x%(5)08x%(4)08x ]
> =C2=A00x00022803=C2=A0=C2=A0CPU%(cpu)d=C2=A0=C2=A0%(tsc)d (+%(reltsc)8d)=
=C2=A0=C2=A0rtds:burn_budget=C2=A0=C2=A0=C2=A0[ dom:vcpu =3D 0x%(1)08x, cur=
_budget =3D 0x%(3)08x%(2)08x, delta =3D %(4)d ]
> -0x00022804=C2=A0=C2=A0CPU%(cpu)d=C2=A0=C2=A0%(tsc)d (+%(reltsc)8d)=C2=A0=
=C2=A0rtds:repl_budget=C2=A0=C2=A0=C2=A0[ dom:vcpu =3D 0x%(1)08x, cur_deadl=
ine =3D 0x%(3)08x%(2)08x, cur_budget =3D 0x%(5)08x%(4)08x ]
> +0x00022804=C2=A0=C2=A0CPU%(cpu)d=C2=A0=C2=A0%(tsc)d (+%(reltsc)8d)=C2=A0=
=C2=A0rtds:repl_budget=C2=A0=C2=A0=C2=A0[ dom:vcpu =3D 0x%(1)08x, priority_=
level =3D 0x%(2)08d cur_deadline =3D 0x%(4)08x%(3)08x, cur_budget =3D 0x%(6=
)08x%(5)08x ]
>
Why 0x%(2)08d, and not just %(2)d ?

Have you tested it? What does it print?

Dario
--=20
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
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